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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
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* Added tail call optimization to the x86 back end. It can beArnold Schwaighofer2007-10-111-0/+2
| | | | | | | | | | | enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
* Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.Evan Cheng2007-10-091-6/+13
| | | | llvm-svn: 42783
* Allow x86 compare to be commutable by default.Evan Cheng2007-10-081-9/+0
| | | | llvm-svn: 42761
* Commute x86 cmove instructions by swapping the operands and change the conditionEvan Cheng2007-10-051-1/+101
| | | | | | | to its inverse. Testing this as llcbeta llvm-svn: 42661
* Enable convertToThreeAddress for X86 by default.Evan Cheng2007-10-051-9/+0
| | | | llvm-svn: 42655
* INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still canEvan Cheng2007-10-051-8/+4
| | | | | | cause performance degradation. llvm-svn: 42653
* In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.Evan Cheng2007-10-051-89/+98
| | | | | | leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
* Add support to convert more 64-bit instructions to 3-address instructions.Evan Cheng2007-10-051-8/+25
| | | | llvm-svn: 42642
* Testing convertToThreeeAddress as X86 llcbeta.Evan Cheng2007-10-051-5/+24
| | | | llvm-svn: 42630
* Enabling new condition code modeling scheme.Evan Cheng2007-09-291-56/+16
| | | | llvm-svn: 42459
* Added support for new condition code modeling scheme (i.e. physical register ↵Evan Cheng2007-09-251-16/+57
| | | | | | | | dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
* Add 64-bit jmp instructions to the list of instructions thatDan Gohman2007-09-171-0/+2
| | | | | | can terminate a block with no fall-through. llvm-svn: 42029
* Add patterns for SHLD64* and SHRD64*.Dan Gohman2007-09-141-1/+5
| | | | llvm-svn: 41975
* Add implicit def of EFLAGS on those instructions that may modify flags.Evan Cheng2007-09-141-12/+12
| | | | llvm-svn: 41962
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:Evan Cheng2007-09-061-25/+15
| | | | | | | | leal (,%rcx,8), %rcx It should be leal (,%rcx,8), %ecx llvm-svn: 41735
* Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via ↵Christopher Lamb2007-08-101-10/+47
| | | | | | subregisters when 16-bit LEA is disabled. llvm-svn: 41007
* Don't pollute the meaning of isUnpredicatedTerminator.Evan Cheng2007-07-261-7/+12
| | | | llvm-svn: 40537
* isUnpredicatedTerminator should treat conditional branches as unpredicated ↵Evan Cheng2007-07-061-2/+9
| | | | | | terminator. llvm-svn: 37960
* Refactor X87 instructions. As a side effect, allDale Johannesen2007-07-041-5/+5
| | | | | | their names are changed. llvm-svn: 37876
* Fix for PR 1505 (and 1489). Rewrite X87 registerDale Johannesen2007-07-031-1/+2
| | | | | | | model to include f32 variants. Some factoring improvments forthcoming. llvm-svn: 37847
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-13/+4
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+13
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Do not treat FP_REG_KILL as terminator in branch analysis (X86).Dale Johannesen2007-06-141-4/+10
| | | | llvm-svn: 37578
* Add a target hook to allow loads from constant pools to be rematerialized, ↵Dan Gohman2007-06-141-0/+25
| | | | | | | | and an implementation for x86. llvm-svn: 37576
* Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen2007-06-131-0/+10
| | | | llvm-svn: 37571
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-2/+2
| | | | llvm-svn: 37528
* BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng2007-05-211-0/+5
| | | | | | instruction. llvm-svn: 37266
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-9/+12
| | | | | | / inserted. llvm-svn: 37193
* Relex assertions to account for additional implicit def / use operands.Evan Cheng2007-04-251-1/+1
| | | | llvm-svn: 36430
* Remove some invalid instructions from this check.Bill Wendling2007-04-241-2/+1
| | | | llvm-svn: 36404
* Adding more MMX instructions.Bill Wendling2007-04-031-1/+3
| | | | llvm-svn: 35638
* Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.Bill Wendling2007-04-031-5/+5
| | | | llvm-svn: 35616
* Compile CodeGen/X86/lea-3.ll:test2 to:Chris Lattner2007-03-281-0/+13
| | | | | | | | | | | | | | | | _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
* Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to theChris Lattner2007-03-281-1/+3
| | | | | | system assembler not groking legal instructions like "leal (,%esi,8), %ecx". llvm-svn: 35393
* Two changes:Chris Lattner2007-03-201-9/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
* Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so thatBill Wendling2007-03-081-1/+6
| | | | | | moves, loads, etc. are recognized. llvm-svn: 35031
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-8/+0
| | | | llvm-svn: 33537
* convertToThreeAddress() is now responsible for updating live info as well as ↵Evan Cheng2006-12-011-8/+16
| | | | | | inserting the new MI's. llvm-svn: 32097
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-15/+15
| | | | | | of opcode and number of operands. llvm-svn: 31947
* Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.Evan Cheng2006-11-161-3/+1
| | | | llvm-svn: 31794
* Properly transfer kill / dead info.Evan Cheng2006-11-151-14/+27
| | | | llvm-svn: 31765
* Matches MachineInstr changes.Evan Cheng2006-11-131-11/+11
| | | | llvm-svn: 31712
* fix wonky indentationChris Lattner2006-10-301-6/+6
| | | | llvm-svn: 31298
* add another target hook for branch folding.Chris Lattner2006-10-281-0/+12
| | | | llvm-svn: 31262
* Implement support for branch condition reversal.Chris Lattner2006-10-211-2/+28
| | | | llvm-svn: 31099
* Simplify code, no functionality changeChris Lattner2006-10-211-4/+2
| | | | llvm-svn: 31097
* allow insertion of a conditional branch with fall-throughChris Lattner2006-10-211-6/+12
| | | | llvm-svn: 31095
* update assert messageChris Lattner2006-10-211-1/+1
| | | | llvm-svn: 31093
* bugfixChris Lattner2006-10-201-1/+1
| | | | llvm-svn: 31074
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