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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
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* fix a wordo that gordon noticed :)Chris Lattner2008-01-121-1/+1
* Any x86 instruction that reads from an invariant location is invariant.Chris Lattner2008-01-121-43/+24
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-4/+4
* remove xchg and shift-reg-by-1 instructions, which are dead.Chris Lattner2008-01-111-14/+2
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-10/+13
* verify that the frame index is immutable before remat'ing (still disabled)Chris Lattner2008-01-101-7/+10
* add a testcase Chris Lattner2008-01-091-5/+4
* Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.Bill Wendling2008-01-071-13/+9
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-13/+13
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-7/+7
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
* Add predicates methods to TargetOperandInfo, and switch all clients Chris Lattner2008-01-071-4/+4
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-12/+11
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+1031
* Fix comment.Bill Wendling2008-01-051-2/+1
* Chris and Evan noticed that this check was compleatly fubared. I wasBill Wendling2008-01-051-1/+4
* enable sinking and licm of loads from the argument area. I'd like to enable ...Chris Lattner2008-01-051-0/+21
* simplify some code by using shorter accessors.Chris Lattner2008-01-051-17/+17
* revert my previous patch.Chris Lattner2008-01-051-10/+29
* factor some code better to avoid redundancy between Chris Lattner2008-01-051-29/+10
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-0/+41
* Machine LICM will check that operands are defined outside of the loop. AlsoBill Wendling2008-01-021-33/+1
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+142
* Fix a bug in my previous patch: refer to the impl not the pure virtual versio...Chris Lattner2008-01-011-1/+1
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+68
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-4/+4
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-11/+11
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewis...Chris Lattner2007-12-301-12/+12
* If we have a load of a global address that's not modified during theBill Wendling2007-12-301-3/+51
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. IBill Wendling2007-12-171-0/+34
* Reverting 44702. It wasn't correct to rename them.Bill Wendling2007-12-081-1/+1
* Renaming:Bill Wendling2007-12-081-1/+1
* Added tail call optimization to the x86 back end. It can beArnold Schwaighofer2007-10-111-0/+2
* Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.Evan Cheng2007-10-091-6/+13
* Allow x86 compare to be commutable by default.Evan Cheng2007-10-081-9/+0
* Commute x86 cmove instructions by swapping the operands and change the conditionEvan Cheng2007-10-051-1/+101
* Enable convertToThreeAddress for X86 by default.Evan Cheng2007-10-051-9/+0
* INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still canEvan Cheng2007-10-051-8/+4
* In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.Evan Cheng2007-10-051-89/+98
* Add support to convert more 64-bit instructions to 3-address instructions.Evan Cheng2007-10-051-8/+25
* Testing convertToThreeeAddress as X86 llcbeta.Evan Cheng2007-10-051-5/+24
* Enabling new condition code modeling scheme.Evan Cheng2007-09-291-56/+16
* Added support for new condition code modeling scheme (i.e. physical register ...Evan Cheng2007-09-251-16/+57
* Add 64-bit jmp instructions to the list of instructions thatDan Gohman2007-09-171-0/+2
* Add patterns for SHLD64* and SHRD64*.Dan Gohman2007-09-141-1/+5
* Add implicit def of EFLAGS on those instructions that may modify flags.Evan Cheng2007-09-141-12/+12
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
* Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:Evan Cheng2007-09-061-25/+15
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