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* give VZEXT_LOAD a memory operand, it now works with segment registers.Chris Lattner2010-09-221-1/+1
| | | | llvm-svn: 114515
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-2/+4
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* Fix typos. 128-bit PSHUFB takes 128-bit memory op.Dale Johannesen2010-09-131-1/+1
| | | | | | v8i16 is not an MMX type; put it where it belongs. llvm-svn: 113785
* Reapply r113585. The msvc machine is mercurial.Bill Wendling2010-09-101-2/+2
| | | | llvm-svn: 113610
* r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can'tBill Wendling2010-09-101-2/+2
| | | | | | understand (the log file was no help). llvm-svn: 113605
* Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands soBill Wendling2010-09-101-2/+2
| | | | | | | that the memoperands are properly set after DAG building and general mucking about. llvm-svn: 113585
* Remove unused target specific nodeBruno Cardoso Lopes2010-09-071-6/+0
| | | | llvm-svn: 113224
* Use movlps, movlpd, movss and movsd specific nodes instead of pattern ↵Bruno Cardoso Lopes2010-09-011-8/+2
| | | | | | matching with movlp pattern fragment llvm-svn: 112694
* Use x86 specific MOVSLDUP node, add more patterns to match it and remove ↵Bruno Cardoso Lopes2010-08-311-6/+0
| | | | | | useless load nodes llvm-svn: 112661
* Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some ↵Bruno Cardoso Lopes2010-08-311-5/+2
| | | | | | useless nodes llvm-svn: 112642
* This is the first step towards refactoring the x86 vector shuffle code. TheBruno Cardoso Lopes2010-08-201-0/+72
| | | | | | | | | | | | general idea here is to have a group of x86 target specific nodes which are going to be selected during lowering and then directly matched in isel. The commit includes the addition of those specific nodes and a *bunch* of patterns, and incrementally we're going to switch between them and what we have right now. Both the patterns and target specific nodes can change as we move forward with this work. llvm-svn: 111691
* Add comments to some pattern fragments in x86Bruno Cardoso Lopes2010-08-131-4/+10
| | | | llvm-svn: 111041
* Add AVX matching patterns to Packed Bit Test intrinsics.Bruno Cardoso Lopes2010-08-101-2/+3
| | | | | | | | | | | | Apply the same approach of SSE4.1 ptest intrinsics but create a new x86 node "testp" since AVX introduces vtest{ps}{pd} instructions which set ZF and CF depending on sign bit AND and ANDN of packed floating-point sources. This is slightly different from what the "ptest" does. Tests comming with the other 256 intrinsics tests. llvm-svn: 110744
* Patterns to match AVX 256-bit permutation intrinsicsBruno Cardoso Lopes2010-08-061-0/+2
| | | | llvm-svn: 110468
* Add more 256-bit forms for a bunch of regular AVX instructionsBruno Cardoso Lopes2010-07-211-0/+3
| | | | | | | Add 64-bit (GR64) versions of some instructions (which are not described in their SSE forms, but are described in AVX) llvm-svn: 109063
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-0/+1
| | | | llvm-svn: 108769
* Move some SIMD fragment code into X86InstrFragmentsSIMD so that theDavid Greene2010-07-121-0/+336
| | | | | | | utility classes can be used from multiple files. This will aid transitioning to a new refactored x86 SIMD specification. llvm-svn: 108213
* TableGen fragment refactoring.David Greene2010-02-091-0/+62
Move some utility TableGen defs, classes, etc. into a common file so they may be used my multiple pattern files. We will use this for the AVX specification to help with the transition from the current SSE specification. llvm-svn: 95727
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