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* [AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.Craig Topper2016-08-281-0/+1
| | | | llvm-svn: 279951
* [X86] Mark some of the X86 SDNodes as commutative.Craig Topper2016-08-151-8/+10
| | | | llvm-svn: 278653
* [X86] X86ISD::FANDN is not commutative or associative.Craig Topper2016-08-151-2/+1
| | | | llvm-svn: 278652
* [X86] Replace CodeGenOnly VPSRAVW/D/Q_Int instructions with patterns since ↵Craig Topper2016-07-241-1/+3
| | | | | | the operand types exactly match the normal VPSRAVW/D/Q instructions. llvm-svn: 276555
* [X86] Remove dead ISD opcodes. NFC.Ahmed Bougacha2016-06-241-8/+0
| | | | llvm-svn: 273716
* [AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic ↵Igor Breger2016-06-201-0/+2
| | | | | | | | intrinsic lowering. Differential Revision: http://reviews.llvm.org/D20897 llvm-svn: 273138
* [x86, SSE] change patterns for CMPP to float types to allow matching with ↵Sanjay Patel2016-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | SSE1 (PR28044) This patch is intended to solve: https://llvm.org/bugs/show_bug.cgi?id=28044 By changing the definition of X86ISD::CMPP to use float types, we allow it to be created and pass legalization for an SSE1-only target where v4i32 is not legal. The motivational trail for this change includes: https://llvm.org/bugs/show_bug.cgi?id=28001 and eventually makes this trigger: http://reviews.llvm.org/D21190 Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86 intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86 intrinsics, a big pile of generic optimizations can trigger. Differential Revision: http://reviews.llvm.org/D21235 llvm-svn: 272511
* [X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructionsSimon Pilgrim2016-06-031-1/+6
| | | | | | | | | | | | This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage. The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls. Mask decoding/target shuffle support will be added in future patches. Differential Revision: http://reviews.llvm.org/D20049 llvm-svn: 271633
* [X86] Define segment MI operands as regs instead of i8imm.Ahmed Bougacha2016-06-021-2/+2
| | | | | | | | | | | | | | | | | | | We've been pretending that segments are i8imm since the initial support (r68645), predating the addition of the SEGMENT_REG class (r81895). That happens to works, but is wrong, and inconsistent with how we print (e.g., X86ATTInstPrinter::printMemReference) and parse them (e.g., X86Operand::addMemOperands). This change shouldn't affect any tool users, but is visible to library users or out-of-tree tablegen backends: this causes MCOperandInfo for the segment op to have an RC instead of "unknown", and TII::getRegClass to actually return something. As the registers are reserved and no vregs of the class ever created, that shouldn't change anything. No test change; no suspicious getRegClass() in X86 and CodeGen. llvm-svn: 271559
* [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.Michael Zuckerman2016-05-211-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D20438 llvm-svn: 270322
* [Clang][AVX512][intrinsics] Fix vscalef intrinsics.Michael Zuckerman2016-05-211-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20324 llvm-svn: 270321
* [X86] Generalize and combine some similar type constraints and node types. ↵Craig Topper2016-05-191-46/+15
| | | | | | No changes to the isel table size so the separation wasn't buying us anything. llvm-svn: 270026
* [X86] Simplify some type constraints by removing parts that were already ↵Craig Topper2016-05-191-12/+5
| | | | | | implied. llvm-svn: 270025
* [X86] Remove some type constraint classes and use already existing stricter ↵Craig Topper2016-05-191-16/+10
| | | | | | classes. llvm-svn: 270013
* [AVX512] Strengthen type constraints for VFIXUPIMM patterns and combine the ↵Craig Topper2016-05-191-7/+8
| | | | | | type constraints for vector and scalar. llvm-svn: 270012
* [AVX512] Strengthen type constraints on my rounding mode inputs and some ↵Craig Topper2016-05-181-16/+23
| | | | | | immediate inputs. llvm-svn: 269886
* [AVX512] Strengthen type checks on the X86ISD::SELECT node. Saves over 800 ↵Craig Topper2016-05-181-1/+10
| | | | | | bytes in the DAG isel table by removing type checks for the condition operand which is always a vector or scalar of i1 matching the the number of elements in the other operands. llvm-svn: 269885
* [X86] Strengthen some type contraints for floating point round and extend.Craig Topper2016-05-091-14/+10
| | | | llvm-svn: 268892
* [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round ↵Craig Topper2016-05-091-16/+16
| | | | | | and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result. llvm-svn: 268891
* [X86][SSE] Dropped X86ISD::FGETSIGNx86 and use MOVMSK instead for FGETSIGN ↵Simon Pilgrim2016-05-021-1/+0
| | | | | | | | lowering movmsk.ll tests are unchanged. llvm-svn: 268237
* [X86][SSE] Support for MOVMSK signbit extraction instructionsSimon Pilgrim2016-04-031-0/+3
| | | | | | | | | | Add support for lowering with the MOVMSK instruction to extract vector element signbits to a GPR. This is an early step towards more optimal handling of vector comparison results. Differential Revision: http://reviews.llvm.org/D18741 llvm-svn: 265266
* [X86][XOP] Support for VPPERM byte shuffle instructionSimon Pilgrim2016-03-241-0/+4
| | | | | | | | This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode. Differential Revision: http://reviews.llvm.org/D18189 llvm-svn: 264260
* AVX512: Combine AND + TESTM instructions .Igor Breger2016-03-031-8/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D17844 llvm-svn: 262621
* [X86] Remove the now-unused X86ISD::PSIGN. NFC.Ahmed Bougacha2016-02-161-3/+0
| | | | llvm-svn: 261025
* [X86][AVX512] add intrinsics of Scalar FP to integer conversion with ↵Asaf Badouh2016-02-071-0/+6
| | | | | | | | rounding mode Differential Revision: http://reviews.llvm.org/D16629 llvm-svn: 260033
* [X86][AVX] Add support for 64-bit VZEXT_LOAD of 256/512-bit vectors to ↵Simon Pilgrim2016-02-031-5/+0
| | | | | | | | | | | | EltsFromConsecutiveLoads Follow up to D16217 and D16729 This change uncovered an odd pattern where VZEXT_LOAD v4i64 was being lowered to a load of the lower v2i64 (so the 2nd i64 destination element wasn't being zeroed), I can't find any use/reason for this and have removed the pattern and replaced it so only the 1st i64 element is loaded and the upper bits all zeroed. This matches the description for X86ISD::VZEXT_LOAD Differential Revision: http://reviews.llvm.org/D16768 llvm-svn: 259635
* fix typos; NFCSanjay Patel2016-02-011-2/+2
| | | | llvm-svn: 259438
* [X86][AVX512VBMI] add encoding and intrinsics for MultishiftAsaf Badouh2016-02-011-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D16399 llvm-svn: 259363
* [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned ↵Asaf Badouh2016-01-251-0/+3
| | | | | | | | | | | 52bit integer VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators Differential Revision: http://reviews.llvm.org/D16407 llvm-svn: 258680
* [X86][AVX512]fix dag & add intrinsics for fixupimmAsaf Badouh2016-01-191-1/+6
| | | | | | | | cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics Differential Revision: http://reviews.llvm.org/D16313 llvm-svn: 258124
* [AVX512] adding PRORQ , PRORD , PRORLVQ and PRORLVD Intrinsics Michael Zuckerman2016-01-131-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16052 llvm-svn: 257594
* [AVX512] adding PROLQ and PROLD IntrinsicsMichael Zuckerman2016-01-121-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D16048 llvm-svn: 257523
* AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE.Igor Breger2015-12-271-0/+2
| | | | | | | | | Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB. Implement VPMOVB/W/D/Q2M intrinsic. Differential Revision: http://reviews.llvm.org/D15675 llvm-svn: 256470
* Start replacing vector_extract/vector_insert with extractelt/inserteltMatt Arsenault2015-12-111-4/+4
| | | | | | | | | | | | | | | | | | | | These are redundant pairs of nodes defined for INSERT_VECTOR_ELEMENT/EXTRACT_VECTOR_ELEMENT. insertelement/extractelement are slightly closer to the corresponding C++ node name, and has stricter type checking so prefer it. Update targets to only use these nodes where it is trivial to do so. AArch64, ARM, and Mips all have various type errors on simple replacement, so they will need work to fix. Example from AArch64: def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; Which is trying to do sext_inreg i8, i8. llvm-svn: 255359
* [X86][AVX512] add comi with SaeAsaf Badouh2015-12-021-0/+4
| | | | | | | | add builtin_ia32_vcomisd and builtin_ia32_vcomisd Differential Revision: http://reviews.llvm.org/D14331 llvm-svn: 254493
* [AVX512] The vpermi2 instructions require an integer vector for the index ↵Craig Topper2015-11-301-3/+7
| | | | | | | | vector. This is reflected correctly in the intrinsics, but was not refelected in the isel patterns. For the floating point types, this requires adding a bitcast to the index vector when its passed through to the output. llvm-svn: 254277
* [X86] int_x86_avx2_permps and X86ISD::VPERMV should take an integer vector ↵Craig Topper2015-11-291-1/+5
| | | | | | for its shuffle indices. llvm-svn: 254269
* [X86] Merge X86VPermt2Fp and X86VPermt2Int back together by weakening them ↵Craig Topper2015-11-261-6/+2
| | | | | | just enough. The SDTCisSameSizeAs introduced in r254138 helps here. llvm-svn: 254176
* [X86] Split ISD node for Vfpclass and Vfpclasss so that we can write strong ↵Craig Topper2015-11-261-3/+6
| | | | | | type constraints for each that don't cause ambiguous isel. llvm-svn: 254172
* [X86] Revert part of r254167 to recover bots.Craig Topper2015-11-261-6/+3
| | | | llvm-svn: 254169
* [X86] Strengthen more type constraints to reduce isel table size.Craig Topper2015-11-261-12/+24
| | | | llvm-svn: 254167
* [X86] Strengthen more type constraints to reduce isel table size.Craig Topper2015-11-261-21/+33
| | | | llvm-svn: 254142
* [X86] Strengthen the type constraints on X86psadbw and X86dbpsadbw to reduce ↵Craig Topper2015-11-261-2/+6
| | | | | | some of the type checks in the isel matching tables. llvm-svn: 254139
* AVX-512: Fixed a bug in VPERMT2* intrinsic.Elena Demikhovsky2015-11-251-2/+11
| | | | | | | | | It was wrong order of operands (from intrinsic to DAG node). I added more strict type specification for instruction selection. Differential Revision: http://reviews.llvm.org/D14942 llvm-svn: 254059
* [X86] Fix several issues related to X86's psadbw instruction.Cong Hou2015-11-241-2/+2
| | | | | | | | | | | | | | | | This patch fixes the following issues: 1. Fix the return type of X86psadbw: it should not be the same type of inputs. For vNi8 inputs the output should be vMi64, where M = N/8. 2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly. 3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly. 4. Adjust the return type when building a DAG node of X86ISD::PSADBW type. 5. Update related tests. Differential revision: http://reviews.llvm.org/D14897 llvm-svn: 254010
* [X86][AVX512CD] add mask broadcast intrinsicsAsaf Badouh2015-11-181-1/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D14573 llvm-svn: 253450
* revert rev. 252153 due to build failure on ubuntuAsaf Badouh2015-11-051-4/+0
| | | | | | [X86][AVX512] add comi with Sae llvm-svn: 252154
* [X86][AVX512] add comi with SaeAsaf Badouh2015-11-051-0/+4
| | | | | | | | add builtin_ia32_vcomisd and builtin_ia32_vcomisd Differential Revision: http://reviews.llvm.org/D14331 llvm-svn: 252153
* AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and ↵Igor Breger2015-11-021-0/+4
| | | | | | | | VBROADCASTF32x2 instructions. Differential Revision: http://reviews.llvm.org/D14216 llvm-svn: 251781
* [X86][AVX512] [X86][AVX512] add convert float to halfAsaf Badouh2015-10-271-0/+5
| | | | | | | | convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem). Differential Revision: http://reviews.llvm.org/D14113 llvm-svn: 251409
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