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* [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> froundMichael Kuperstein2016-08-181-6/+6
| | | | | | | | | | The names of the tablegen defs now match the names of the ISD nodes. This makes the world a slightly saner place, as previously "fround" matched ISD::FP_ROUND and not ISD::FROUND. Differential Revision: https://reviews.llvm.org/D23597 llvm-svn: 279129
* [X86] Remove many operands that represent memory stores from outs to ins. ↵Craig Topper2016-03-131-5/+5
| | | | | | These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs. llvm-svn: 263354
* By intel specMichael Zuckerman2015-12-021-1/+1
| | | | | | | | | | | | | |9B DD /7| FSTSW m2byte| Valid Valid Store FPU status word at m2byteafter checking for pending unmasked floating-point exceptions.| |9B DF E0| FSTSW AX| Valid Valid Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.| |DD /7 |FNSTSW *m2byte| Valid Valid Store FPU status word at m2bytewithout checking for pending unmasked floating-point exceptions.| |DF E0 |FNSTSW *AX| Valid Valid Store FPU status word in AX register without checking for pending unmasked floating-point exceptions| m2byte is word register, and therefor instruction operand need to be change from f32mem to i16mem. Differential Revision: http://reviews.llvm.org/D14953 llvm-svn: 254512
* [X86] Fix patterns for memory forms of FP FSUBR and FDIVR. They need to have ↵Craig Topper2015-12-011-39/+69
| | | | | | | | memory on the left hand side of the fsub/fdiv operations in their patterns. Not sure how to test this. I noticed by inspection in the isel tables where the same pattern tried to produce DIV and DIVR or SUB and SUBR. llvm-svn: 254388
* [X86] Add fxsr feature flag for fxsave/fxrestore instructions.Craig Topper2015-10-161-10/+12
| | | | llvm-svn: 250497
* [X86] Fix FBLD and FBSTPMarina Yatsina2015-08-201-2/+2
| | | | | | | | | | FBLD and FBSTP should receive TBYTE because it is defined as FBLD m80 FBSTP m80 Differential Revision: http://reviews.llvm.org/D11748 llvm-svn: 245553
* [X86] Add FXSR intrinsicsMichael Kuperstein2015-06-301-8/+8
| | | | | | Add intrinsics for the FXSR instructions (FXSAVE/FXSAVE64/FXRSTOR/FXRSTOR64) llvm-svn: 241049
* Change x86 CMOVE_F to read it source, not write it.Pete Cooper2015-04-291-8/+8
| | | | | | | | | | This was breaking sqlite with the machine verifier because operand 0 was a def according to tablegen, but didn't have the 'isDef' flag set. Looking at the ISA, its clear that this operand is a source as writing to st(0) is implicit. So move the operand to the correct place in the td file. rdar://problem/20751584 llvm-svn: 236183
* [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T ↵Craig Topper2015-02-031-2/+2
| | | | | | syntax. Also make them the default output. llvm-svn: 227963
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-38/+38
| | | | llvm-svn: 223339
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-3/+3
| | | | llvm-svn: 222801
* [X86] Simplify X87 stackifier pass.Akira Hatanaka2014-08-011-3/+0
| | | | | | | | | | | | | | | | | | | Stop using ST registers for function returns and inline-asm instructions and use FP registers instead. This allows removing a large amount of code in the stackifier pass that was needed to track register liveness and handle copies between ST and FP registers and function calls returning floating point values. It also fixes a bug which manifests when an ST register defined by an inline-asm instruction was live across another inline-asm instruction, as shown in the following sequence of machine instructions: 1. INLINEASM <es:frndint> $0:[regdef], %ST0<imp-def,tied5> 2. INLINEASM <es:fldcw $0> 3. %FP0<def> = COPY %ST0 <rdar://problem/16952634> llvm-svn: 214580
* [X86] Set the scheduling resources of some of the FPStack instructions.Quentin Colombet2014-03-121-0/+17
| | | | | | This is related to <rdar://problem/15607571>. llvm-svn: 203682
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-37/+37
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Switch a few instructions to use RI instead I so they don't require REX_W to ↵Craig Topper2014-01-171-5/+5
| | | | | | be explicitly specified. llvm-svn: 199479
* Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix ↵Craig Topper2014-01-171-2/+2
| | | | | | instead of 'q' llvm-svn: 199474
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-011-71/+62
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-311-62/+71
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-301-71/+62
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-15/+15
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Remove some errant space charcters in mnemonic strings.Craig Topper2013-07-231-1/+1
| | | | llvm-svn: 186932
* More Intel syntax alias fixes.Craig Topper2013-07-221-1/+1
| | | | llvm-svn: 186814
* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-7/+19
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. llvm-svn: 178050
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-021-65/+89
| | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996
* X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer2012-04-271-9/+24
| | | | | | | | | | | | | | | pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
* some comment fix for X86 and ARMJia Liu2012-02-191-1/+1
| | | | llvm-svn: 150902
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-2/+2
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-101-18/+11
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. llvm-svn: 147841
* Enable FISTTP* instructions when AVX is enabled.Craig Topper2012-01-081-9/+9
| | | | llvm-svn: 147758
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-031-14/+14
| | | | llvm-svn: 147453
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-281-38/+2
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. llvm-svn: 134018
* Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.Reid Kleckner2011-02-121-0/+4
| | | | | | | | These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. llvm-svn: 125446
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-2/+2
| | | | llvm-svn: 122513
* Move X86InstrFPStack.td over to PseudoI as well.Eric Christopher2010-11-301-27/+9
| | | | llvm-svn: 120470
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-061-2/+2
| | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-061-4/+4
| | | | | | | listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
* Reverting r117031 to cleanup valgrind errors.Andrew Trick2010-10-221-3/+3
| | | | | | | It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. llvm-svn: 117087
* More tweaks to X86 instructions to allow the 'w' suffix in places it makesKevin Enderby2010-10-211-3/+3
| | | | | | | | | sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Also added the missing flex (without the wait prefix) and ud2a as an alias to ud2 (still to add ud2b). llvm-svn: 117031
* allow !strconcat to take more than two operands to eliminateChris Lattner2010-10-051-4/+4
| | | | | | | | !strconcat(!strconcat(!strconcat(!strconcat Simplify some x86 td files to use it. llvm-svn: 115719
* refactor .td files a bit, moving system instructions out to X86InstrSystem.tdChris Lattner2010-10-051-3/+4
| | | | llvm-svn: 115591
* convert the last 4 X86ISD nodes that should have memoperands to have them.Chris Lattner2010-09-221-4/+6
| | | | llvm-svn: 114523
* give FP_TO_INT16_IN_MEM and friends a memoperand. They are onlyChris Lattner2010-09-221-4/+5
| | | | | | used with stack slots, but hey, lets be safe. llvm-svn: 114521
* Fix comment typos.Bob Wilson2010-08-261-1/+1
| | | | llvm-svn: 112202
* Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKillJakob Stoklund Olesen2010-07-161-4/+0
| | | | | | | | | pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. llvm-svn: 108536
* Use target independent COPY instructions for the fake fextend and froundJakob Stoklund Olesen2010-07-111-6/+6
| | | | | | operations in x87 code. llvm-svn: 108098
* Remove isTwoAddress from here too.Eric Christopher2010-06-181-2/+2
| | | | llvm-svn: 106358
* Changed llvm-mc to use the same suffixes with floating point compareKevin Enderby2010-05-031-6/+6
| | | | | | | instructions as the Mac OS X darwin assembler. Some of which like 'fcoml' assembled to different opcodes. While some of the suffixes were just different. llvm-svn: 102958
* Now that tblgen can handle matching implicit defs of instructionsChris Lattner2010-03-191-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
* add support for pentium class CPUs which do not have cmov,Chris Lattner2010-03-141-3/+12
| | | | | | PR4841. Patch by Craig Smith! llvm-svn: 98496
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-271-1/+1
| | | | llvm-svn: 97348
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