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* fix a case where we'd mis-encode fisttp because of an incorrect (andChris Lattner2010-02-051-1/+0
| | | | | | redundant with a correct one) pattern that was added for the disassembler. llvm-svn: 95446
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-181-28/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Removed a few instructions that were alreadySean Callanan2009-09-161-5/+0
| | | | | | covered by other definitions. llvm-svn: 81992
* Added a variety of floating-point and SSE instructions.Sean Callanan2009-09-161-0/+30
| | | | | | | | | | | | All of these do not have patterns (they're for the disassembler). Many of the floating-point instructions will probably be rolled into definitions that have patterns, and may eventually be superseded by mdefs. So I put them together and left a comment. llvm-svn: 81979
* Implement FpSET_ST1_*.Evan Cheng2009-02-091-0/+6
| | | | llvm-svn: 64186
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Use ## for comment delimiter on darwin x86-32, soDale Johannesen2008-03-251-10/+10
| | | | | | | | llvm's output .s files will go through gcc -std=c99 without triggering preprocesser errors. Approach suggested by Daveed Vandevoorde. llvm-svn: 48808
* remove Evan's "ugly hack" that sorta attempted to get Chris Lattner2008-03-211-4/+0
| | | | | | | x86-64 return conventions correct, but was never enabled. We can now do the "right thing" with multiple return values. llvm-svn: 48635
* Add support for calls that return two FP values inChris Lattner2008-03-211-0/+9
| | | | | | ST(0)/ST(1). llvm-svn: 48634
* Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to Chris Lattner2008-03-101-20/+6
| | | | | | copyfromreg/copytoreg instead. llvm-svn: 48174
* rename FP_SETRESULT -> FP_SET_ST0Chris Lattner2008-03-091-7/+7
| | | | llvm-svn: 48094
* rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support forChris Lattner2008-03-091-26/+38
| | | | | | | isel'ing value preserving FP roundings from one fp stack reg to another into a noop, instead of stack traffic. llvm-svn: 48093
* Work in progress. This patch *fixes* x86-64 calls which are modelled as ↵Evan Cheng2008-01-291-0/+7
| | | | | | | | StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results. Status: This only works for direct calls, and only the caller side is done. Disabled for now. llvm-svn: 46527
* more flags set rightChris Lattner2008-01-111-13/+15
| | | | llvm-svn: 45860
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-18/+30
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* remove explicit sets of 'neverHasSideEffects' that can now be Chris Lattner2008-01-101-1/+1
| | | | | | inferred from the instr patterns. llvm-svn: 45824
* get def use info more correct.Chris Lattner2008-01-101-4/+4
| | | | llvm-svn: 45821
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. IBill Wendling2007-12-171-2/+2
| | | | | | | | | based what flag to set on whether it was already marked as "isRematerializable". If there was a further check to determine if it's "really" rematerializable, then I marked it as "mayHaveSideEffects" and created a check in the X86 back-end similar to the remat one. llvm-svn: 45132
* LD_Fp64m should have "isRematerializable" set.Bill Wendling2007-12-171-1/+2
| | | | llvm-svn: 45128
* Implement codegen for flt_rounds on x86Anton Korobeynikov2007-11-161-1/+6
| | | | llvm-svn: 44183
* Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer2007-10-121-1/+1
| | | | | | | for fastcc from X86CallingConv.td. This means that nested functions are not supported for calling convention 'fastcc'. llvm-svn: 42934
* Enabling new condition code modeling scheme.Evan Cheng2007-09-291-50/+15
| | | | llvm-svn: 42459
* New style x87 cmp instructions.Evan Cheng2007-09-251-0/+18
| | | | llvm-svn: 42312
* Added support for new condition code modeling scheme (i.e. physical register ↵Evan Cheng2007-09-251-0/+25
| | | | | | | | dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
* Fix PR 1681. When X86 target uses +sse -sse2,Dale Johannesen2007-09-231-66/+69
| | | | | | | | | | keep f32 in SSE registers and f64 in x87. This is effectively a new codegen mode. Change addLegalFPImmediate to permit float and double variants to do different things. Adjust callers. llvm-svn: 42246
* Add implicit def of EFLAGS on those instructions that may modify flags.Evan Cheng2007-09-141-1/+1
| | | | llvm-svn: 41962
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-9/+14
| | | | llvm-svn: 41863
* Mark load instructions with isLoad = 1.Evan Cheng2007-08-301-0/+2
| | | | llvm-svn: 41595
* Long double patch 8 of N: make it partially work inDale Johannesen2007-08-071-53/+50
| | | | | | | | | | | SSE mode (all but conversions <-> other FP types, I think): >>Do not mark all-80-bit operations as "Requires[FPStack]" (which really means "not SSE"). >>Refactor load-and-extend to facilitate this. >>Update comments. >>Handle long double in SSE when computing FP_REG_KILL. llvm-svn: 40906
* Long double patch 7 of N, unless I lost count:). Dale Johannesen2007-08-071-0/+24
| | | | | | | | Last x87 bits for full functionality (not thoroughly tested, and long doubles do not work in SSE modes at all - use -mcpu=i486 for now) llvm-svn: 40886
* Get X86 long double calling convention to workDale Johannesen2007-08-061-0/+6
| | | | | | | (on Darwin, anyway). Fix some table omissions for LD arithmetic. llvm-svn: 40877
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-4/+75
| | | | | | Lots of problems yet but some simple things work. llvm-svn: 40847
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-311-57/+57
| | | | | | | | | mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc ↵Evan Cheng2007-07-311-11/+0
| | | | | | (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
* No more noResults.Evan Cheng2007-07-211-6/+5
| | | | llvm-svn: 40132
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-118/+119
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Fix fp_constant_op failure.Dale Johannesen2007-07-101-0/+3
| | | | llvm-svn: 38514
* fix 80 columnn violations, increasing the world'sDale Johannesen2007-07-101-19/+28
| | | | | | pedantic satisfaction level. llvm-svn: 38512
* Refactor X87 instructions. As a side effect, allDale Johannesen2007-07-041-374/+198
| | | | | | their names are changed. llvm-svn: 37876
* Some spacing fixes. Cosmetic.Dale Johannesen2007-07-031-183/+183
| | | | llvm-svn: 37853
* Fix for PR 1505 (and 1489). Rewrite X87 registerDale Johannesen2007-07-031-160/+303
| | | | | | | model to include f32 variants. Some factoring improvments forthcoming. llvm-svn: 37847
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+2
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-2/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Mark re-materializable instructions.Evan Cheng2007-03-211-0/+2
| | | | llvm-svn: 35230
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-1/+1
| | | | llvm-svn: 30945
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-1/+1
| | | | llvm-svn: 30844
* Handle BUILD_VECTOR with all zero elements.Evan Cheng2006-03-241-4/+0
| | | | llvm-svn: 27056
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