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* [X86] Fix some cases where some 8-bit instructions were marked as being ↵Craig Topper2014-12-291-18/+24
| | | | | | convertible to three address instructions, but aren't really. llvm-svn: 224940
* [X86] Add the 0x82 instructions to the disassebmler. They are identical in ↵Craig Topper2014-12-291-6/+35
| | | | | | functionality to the 0x80 opcode instructions, but are not valid in 64-bit mode. llvm-svn: 224939
* [x86] Refactor some tablegen instruction info classes slightly to prepare ↵Craig Topper2014-12-291-29/+28
| | | | | | for another change. NFC. llvm-svn: 224938
* [x86] Remove unused classes from tablegen instruction info.Craig Topper2014-12-291-23/+0
| | | | llvm-svn: 224937
* [X86] Remove unnecessary 'In64BitMode' predicate for instructions that ↵Craig Topper2014-12-181-14/+11
| | | | | | already indicate use of REX.W. llvm-svn: 224495
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-1/+1
| | | | llvm-svn: 223339
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-8/+8
| | | | llvm-svn: 222801
* [x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.Robert Khasanov2014-08-211-20/+28
| | | | llvm-svn: 216162
* [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.Akira Hatanaka2014-07-101-2/+4
| | | | | | | | | Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-2/+2
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-75/+69
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-9/+9
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* Switch a few instructions to use RI instead I so they don't require REX_W to ↵Craig Topper2014-01-171-8/+8
| | | | | | be explicitly specified. llvm-svn: 199479
* Add OpSize16 to the two byte forms of INC/DEC that we only use in 64-bit ↵Craig Topper2014-01-151-5/+5
| | | | | | mode and a 64-bit only LEA. Even though we'll not be in 16-bit mode when we use them it makes their tables consistent with their 32-bit counterparts. llvm-svn: 199297
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-4/+4
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-081-31/+40
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-051-2/+3
| | | | | | and remove disassmbler table emitter hack. llvm-svn: 198544
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-0/+2
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-13/+13
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
| | | | llvm-svn: 192086
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-28/+40
| | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-16/+16
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick2013-06-211-4/+4
| | | | llvm-svn: 184566
* Correct the def registers for the 8bit x86 divide instructions toEric Christopher2013-06-111-4/+4
| | | | | | | match the comments and what the instruction actually does. Noticed on inspection. llvm-svn: 183809
* X86: Fix Defs/Uses for insts that imp-def/imp-use both an A-register and EFLAGS.Ahmed Bougacha2013-05-291-66/+74
| | | | | | | | | | | | | This corrects a problem where x86 instructions that implicitly define/use both an A-register (RAX, EAX, ..) and EFLAGS were declared as only defining/using EFLAGS, because the outer "let Defs/Uses = [EFLAGS]" in the various multiclasses overrides the "let Defs/Uses = [areg]" in BinOpAI. The instructions deriving from BinOpAI were moved out of the "let Defs", and a BinOpAI_FF class was created, for instructions that implicitly define and use EFLAGS and the A-register (SBC, ADC). llvm-svn: 182883
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-2/+2
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. llvm-svn: 178051
* Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen2013-03-201-5/+10
| | | | llvm-svn: 177539
* Annotate X86 arithmetic instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-181-60/+112
| | | | | | | | | This new-style scheduling information is going to replace the instruction iteneraries. This also serves as a test case for Andy's fix in r177317. llvm-svn: 177323
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+46
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* Two changes relevant to LEA and x32:David Sehr2013-02-011-2/+2
| | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
* Remove # from the beginning and end of def names.Craig Topper2013-01-071-123/+123
| | | | llvm-svn: 171696
* Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions ↵Craig Topper2013-01-051-1/+1
| | | | | | hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. llvm-svn: 171608
* Revert "Mark DIV/IDIV instructions hasSideEffects=1 because they can trap ↵Michael Gottesman2013-01-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks." This reverts commit r171461 since it breaks the following tests: Clang :: Analysis/outofbound-notwork.c Clang :: Analysis/string-fail.c Clang :: CXX/basic/basic.lookup/basic.lookup.qual/p6-0x.cpp Clang :: CXX/basic/basic.lookup/basic.lookup.unqual/p15.cpp Clang :: CXX/dcl.dcl/dcl.spec/dcl.fct.spec/p4.cpp Clang :: CXX/dcl.dcl/dcl.spec/dcl.stc/p10.cpp Clang :: CXX/temp/temp.param/p14.cpp Clang :: CXX/temp/temp.res/temp.dep.res/temp.point/p1.cpp Clang :: CodeGen/2009-02-13-zerosize-union-field-ppc.c Clang :: CodeGen/blocks-2.c Clang :: CodeGen/libcalls-d.c Clang :: CodeGen/libcalls-ld.c Clang :: CodeGenCXX/conversion-function.cpp Clang :: CodeGenCXX/debug-info-limit-type.cpp Clang :: CodeGenCXX/inheriting-constructor.cpp Clang :: FixIt/fixit-errors.c Clang :: FixIt/fixit-pmem.cpp Clang :: Modules/namespaces.cpp Clang :: PCH/changed-files.c Clang :: PCH/pr4489.c Clang :: PCH/source-manager-stack.c Clang :: Parser/cxx-ambig-decl-expr-xfail.cpp Clang :: SemaCXX/switch-implicit-fallthrough-cxx98.cpp Clang :: SemaTemplate/instantiate-function-1.mm llvm-svn: 171466
* Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when ↵Craig Topper2013-01-031-1/+1
| | | | | | dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. llvm-svn: 171461
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-271-0/+2
| | | | llvm-svn: 171136
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-271-0/+1
| | | | llvm-svn: 171130
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ↵Craig Topper2012-12-261-43/+44
| | | | | | side effects. llvm-svn: 171121
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-261-0/+1
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. llvm-svn: 171118
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper2012-12-171-2/+13
| | | | | | add ANDN to isDefConvertible. llvm-svn: 170305
* X86: enable CSE between CMP and SUBManman Ren2012-08-081-0/+2
| | | | | | | | | | | | | | We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 llvm-svn: 161462
* X86: remove redundant cmp against zero.Manman Ren2012-07-181-1/+1
| | | | | | | | | Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 llvm-svn: 160454
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-061-0/+2
| | | | | | | | For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. llvm-svn: 159838
* Revert r157831Manman Ren2012-06-031-2/+0
| | | | llvm-svn: 157896
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-011-0/+2
| | | | | | | | | | | | | | | This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. llvm-svn: 157831
* This patch adds X86 instruction itineraries, which were missed by thePreston Gurd2012-04-091-28/+30
| | | | | | original patch to add itineraries, to X86InstrArithmetc.td. llvm-svn: 154320
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-94/+133
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-231-0/+24
| | | | llvm-svn: 142738
* Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ↵Craig Topper2011-10-221-5/+5
| | | | | | multiply instructions. llvm-svn: 142737
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-1/+19
| | | | llvm-svn: 141947
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