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* Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.Jakob Stoklund Olesen2011-10-081-0/+6
| | | | | | | | | | | | | In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. llvm-svn: 141499
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-021-19/+34
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-4/+13
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (whichChris Lattner2010-12-201-39/+97
| | | | | | | | | | | | | their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
* it turns out that when ".with.overflow" intrinsics were added to the X86Chris Lattner2010-12-051-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. llvm-svn: 120935
* fix a subtle bug I introduced in my refactoring, where we stopped preferringChris Lattner2010-10-081-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | the i8 versions of instructions in some cases. In test6, we started generating: cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00] ## <MCInst #478 CMP64mi32 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> instead of: cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] ## <MCInst #479 CMP64mi8 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> Fix this and add some comments. llvm-svn: 116053
* convert test to use the existing classes that the multipatternsChris Lattner2010-10-071-99/+48
| | | | | | | | | use. Since TEST is completely different than all other binops, don't define a multipattern for it. This completes factorization of binops. llvm-svn: 115982
* convert cmp to use a multipatternChris Lattner2010-10-071-199/+181
| | | | llvm-svn: 115978
* reduce redundancy between pattern copies.Chris Lattner2010-10-071-49/+53
| | | | llvm-svn: 115968
* the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.Chris Lattner2010-10-071-19/+19
| | | | llvm-svn: 115967
* convert adc/sbb to a multipattern. Because the adde/sube nodes Chris Lattner2010-10-071-310/+150
| | | | | | | | | | | are not defined as returning EFLAGS (like add_flag and friends), the entire multipattern and several of the subclasses need to be cloned. This could be handled through better instantiation support in tblgen, but it isn't meta enough. llvm-svn: 115964
* add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,Chris Lattner2010-10-071-178/+18
| | | | | | allowing us to convert ADD over. deletes 160 lines of .td file. llvm-svn: 115897
* Fix a few issues in ArithBinOpEFLAGS that made it specific to and.Chris Lattner2010-10-071-497/+18
| | | | | | | | | Start using ArithBinOpEFLAGS for OR, XOR, and SUB. This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all defined exactly the same way instead of being close relatives. llvm-svn: 115896
* Convert 'and' to single instance of a multipatternChris Lattner2010-10-071-50/+63
| | | | | | | | | | | which instantiates the 34 versions of and all in one swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not be required, but tblgen's feeble brain explodes when I use Or4<BaseOpc>.V in the multipattern. No change in the generated .inc files. llvm-svn: 115893
* add a new BinOpAI class to represent the immediate form that directly acts ↵Chris Lattner2010-10-071-10/+16
| | | | | | | | | | on EAX. This does change the generated .inc files to include the implicit use/def of eax. Since these instructions are only generated by the assembler and disassembler it doesn't actually matter though. llvm-svn: 115885
* add a bunch of classes for other common patterns.Chris Lattner2010-10-071-60/+51
| | | | | | As usual, no change in generated .inc files. llvm-svn: 115882
* Define a new BinOpRI8 class and use it to define the imm8 versions of and.Chris Lattner2010-10-071-27/+43
| | | | llvm-svn: 115880
* add the pattern operator to match to X86TypeInfo, use this to Chris Lattner2010-10-071-11/+11
| | | | | | convert AND64ri32 to use BinOpRI. llvm-svn: 115878
* enhance X86TypeInfo to include information about the encoding andChris Lattner2010-10-061-20/+36
| | | | | | | | operand kind for immediates. Use these to define a new BinOpRI class and switch AND8/16/32ri over to it. AND64ri32 needs some more refactoring before it can make the switcheroo. llvm-svn: 115752
* add a class for _REV nodes.Chris Lattner2010-10-061-19/+21
| | | | llvm-svn: 115748
* sink more intelligence into the ITy base class. Now it knowsChris Lattner2010-10-061-12/+21
| | | | | | | that i8 operations are even and i16,i32,i64 operations have a low opcode bit set (they are odd). llvm-svn: 115747
* refactor things a bit, now the REX_W and OpSize prefix bytes are inferred ↵Chris Lattner2010-10-061-22/+46
| | | | | | from the type info. llvm-svn: 115745
* with tblgen suitably extended, we can now get the load node from typeinfo.Chris Lattner2010-10-061-6/+6
| | | | llvm-svn: 115744
* lets go all meta and define new X86 type wrappers that declare the associatedChris Lattner2010-10-061-20/+53
| | | | | | | gunk that goes along with an MVT (e.g. reg class, preferred load operation, memory operand) llvm-svn: 115727
* introduce a new BinOpRM class and use it to factor AND*rm. This points outChris Lattner2010-10-061-21/+16
| | | | | | that I need a heavier handed approach to get ultimate factorization. llvm-svn: 115726
* allow !strconcat to take more than two operands to eliminateChris Lattner2010-10-051-2/+2
| | | | | | | | !strconcat(!strconcat(!strconcat(!strconcat Simplify some x86 td files to use it. llvm-svn: 115719
* associate the instruction suffix letter with the integer gpr Chris Lattner2010-10-051-6/+7
| | | | | | register class, and use this to simplify use of BinOpRR. llvm-svn: 115716
* introduce a new BinOpRR class, and convert 4 and instructions to use it.Chris Lattner2010-10-051-19/+12
| | | | llvm-svn: 115715
* Replace a gross hack (the MOV64ri_alt instruction) with a slightly less Chris Lattner2010-10-051-1/+1
| | | | | | gross hack (having the asmmatcher handle the alias). llvm-svn: 115685
* distribute the rest of the contents of X86Instr64bit.td out toChris Lattner2010-10-051-0/+142
| | | | | | the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
* move the rest of the simple 64-bit arithmetic into InstrArithmetic.tdChris Lattner2010-10-051-10/+195
| | | | llvm-svn: 115663
* continue moving 64-bit stuff into X86InstrArithmetic.tdChris Lattner2010-10-051-89/+244
| | | | llvm-svn: 115660
* move 64-bit add and adc to InstrArithmetic.Chris Lattner2010-10-051-10/+83
| | | | llvm-svn: 115632
* rewrote two addr constraints so that they are only set, not set and then ↵Chris Lattner2010-10-051-321/+343
| | | | | | nestedly cleared. llvm-svn: 115631
* split the 32-bit integer arithmetic instructions out to their own file.Chris Lattner2010-10-051-0/+1242
llvm-svn: 115627
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