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* [X86] Use SSE_INTMUL_ITINS_P for the AVX-512 MUL instructions to match their ↵Craig Topper2017-12-261-5/+5
| | | | | | SSE/AVX counterparts. llvm-svn: 321451
* [X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 ↵Craig Topper2017-12-171-1/+1
| | | | | | extractions. llvm-svn: 320937
* [X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32.Craig Topper2017-12-171-6/+0
| | | | | | This allows us to remove some isel patterns that allowed MVT::i8 result type. llvm-svn: 320936
* [X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen ↵Craig Topper2017-12-161-64/+33
| | | | | | | | classes LZCNT/POPCNT. I think when this instruction was first published it was only for a Knights CPU and thus VLX version was missing. llvm-svn: 320910
* [X86] Widen (v2i32 (fp_to_uint v2f64)) to (v8i32 (fp_to_uint v8f64)) during ↵Craig Topper2017-12-151-5/+0
| | | | | | | | legalization if we have AVX512F, but not VLX. NFC Previously we widened it using isel patterns. llvm-svn: 320824
* [X86] Use Ld scheduler classes for instructions with folded loads.Craig Topper2017-12-121-8/+8
| | | | llvm-svn: 320459
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-101-11/+11
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-101-9/+9
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-101-4/+4
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-101-12/+12
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since ↵Craig Topper2017-12-101-2/+2
| | | | | | they can only be selected by intrinsics. llvm-svn: 320283
* [X86] Remove ReadAfterLd from several several rb instructionsCraig Topper2017-12-101-5/+5
| | | | | | | | This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions 'b' here refers to 'sae' not broadcast. These aren't memory instructions. llvm-svn: 320281
* [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. ↵Simon Pilgrim2017-12-091-6/+6
| | | | | | | | NFCI. Requires re-ordering of AVX512_maskable_custom arguments. llvm-svn: 320255
* [X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classesSimon Pilgrim2017-12-081-1/+1
| | | | | | Match VPTERNLOG which these pseudos will eventually alias to llvm-svn: 320154
* [X86][AVX512] Tag mask reg op instruction scheduler classesSimon Pilgrim2017-12-061-57/+65
| | | | llvm-svn: 319945
* [X86][AVX512] Tag scalar insert/extract instruction scheduler classesSimon Pilgrim2017-12-061-17/+22
| | | | | | Classes don't look great but match what we're doing on SSE/AVX llvm-svn: 319920
* [X86][AVX512] Tag aligned/unaligned move instruction scheduler classesSimon Pilgrim2017-12-061-67/+70
| | | | llvm-svn: 319913
* [X86][AVX512] Tag BROADCAST instruction scheduler classesSimon Pilgrim2017-12-061-39/+61
| | | | llvm-svn: 319900
* [X86][AVX512] Drop default NoItinerary arguments that aren't neededSimon Pilgrim2017-12-061-6/+6
| | | | | | Requires reordering of AVX512_maskable_common arguments, but helps track what is still missing itinerary tags llvm-svn: 319890
* [X86][AVX512] Tag Mask<->Vector instructions scheduler classesSimon Pilgrim2017-12-061-2/+4
| | | | llvm-svn: 319887
* [X86][AVX512] Cleanup scalar move scheduler classesSimon Pilgrim2017-12-061-31/+31
| | | | llvm-svn: 319884
* [X86][AVX512] Tag BLENDM instruction scheduler classesSimon Pilgrim2017-12-051-28/+45
| | | | llvm-svn: 319833
* [X86][AVX512] Tag GATHER/SCATTER instruction scheduler classesSimon Pilgrim2017-12-051-3/+5
| | | | | NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed. llvm-svn: 319829
* [X86][AVX512] Tag VPSLLDQ/VPSRLDQ instruction scheduler classesSimon Pilgrim2017-12-051-9/+20
| | | | llvm-svn: 319822
* [X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classesSimon Pilgrim2017-12-051-90/+106
| | | | llvm-svn: 319815
* [X86][AVX512] Tag VNNIW instruction scheduler classesSimon Pilgrim2017-12-051-15/+18
| | | | llvm-svn: 319784
* [X86][AVX512] Drop some default NoItinerary arguments that aren't needed any ↵Simon Pilgrim2017-12-051-9/+10
| | | | | | more llvm-svn: 319782
* [X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classesSimon Pilgrim2017-12-051-22/+25
| | | | llvm-svn: 319772
* [X86][AVX512] Add missing scalar CMPSS/CMPSD logic scheduler classesSimon Pilgrim2017-12-051-16/+21
| | | | llvm-svn: 319770
* [X86][AVX512] Cleanup bit logic scheduler classesSimon Pilgrim2017-12-051-21/+24
| | | | llvm-svn: 319767
* [X86][AVX512] Tag scalar CVT and CMP instruction scheduler classesSimon Pilgrim2017-12-051-104/+117
| | | | llvm-svn: 319765
* [X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classesSimon Pilgrim2017-12-051-42/+60
| | | | | | Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. llvm-svn: 319760
* [X86][AVX512] Cleanup VPCMP scheduler classesSimon Pilgrim2017-12-051-27/+30
| | | | | | Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. llvm-svn: 319758
* [X86][AVX512] Tag VFIXUPIMM instructions scheduler classesSimon Pilgrim2017-12-051-23/+30
| | | | llvm-svn: 319757
* [X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit ↵Craig Topper2017-12-041-0/+40
| | | | | | | | vectors when AVX512 is enabled. These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already. llvm-svn: 319641
* [X86][AVX512] Tag PH2PS/PS2PH conversion instructions scheduler classesSimon Pilgrim2017-12-031-25/+41
| | | | llvm-svn: 319637
* [X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler classSimon Pilgrim2017-12-031-133/+163
| | | | llvm-svn: 319636
* [X86][AVX512] Tag subvector extract/insert instructions scheduler classesSimon Pilgrim2017-12-011-32/+65
| | | | llvm-svn: 319568
* Fix line endings. NFCI.Simon Pilgrim2017-12-011-10/+10
| | | | llvm-svn: 319559
* [X86][AVX512] Tag VPERM2I/VPERM2T instructions scheduler classSimon Pilgrim2017-12-011-48/+64
| | | | llvm-svn: 319558
* [X86][AVX512] Tag VFPCLASS instructions scheduler classSimon Pilgrim2017-12-011-26/+43
| | | | llvm-svn: 319554
* [X86][AVX512] Tag VPSHUFBITQMB instructions scheduler classSimon Pilgrim2017-12-011-9/+12
| | | | llvm-svn: 319553
* [X86][AVX512] Tag VPCOMRESS/VPEXPAND instructions scheduler classesSimon Pilgrim2017-12-011-39/+55
| | | | llvm-svn: 319551
* [X86][AVX512] Tag vshift/vpermv/pshufd/pshufb instructions scheduler classesSimon Pilgrim2017-12-011-107/+124
| | | | llvm-svn: 319540
* [X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classesSimon Pilgrim2017-11-301-70/+90
| | | | llvm-svn: 319433
* [X86][AVX512] Tag binop/rounding/sae instructions scheduler classesSimon Pilgrim2017-11-301-124/+143
| | | | llvm-svn: 319424
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-301-64/+84
| | | | llvm-svn: 319418
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)Simon Pilgrim2017-11-291-64/+53
| | | | | | Accidental commit of incomplete patch llvm-svn: 319346
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-291-53/+64
| | | | llvm-svn: 319338
* [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions ↵Simon Pilgrim2017-11-291-76/+91
| | | | | | scheduler classes llvm-svn: 319337
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