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* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-181-0/+29
| | | | | | | | | | | Note that I followed the AVX2 convention here and didn't add LLVM intrinsics for stores. These can be generated with the nontemporal hint on LLVM IR stores (see new test). The GCC builtins are lowered directly into nontemporal stores. <rdar://problem/17082571> llvm-svn: 211176
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-181-1/+1
| | | | | | | Use the max 64-bit element size with EVEX_CD8. This should work since element size is ignored for a full-vector access (FVM). llvm-svn: 211175
* Add pattern for unsigned v4i32->v4f64 convert on AVX512.Cameron McInally2014-06-181-0/+4
| | | | llvm-svn: 211164
* Hook up vector int_ctlz for AVX512.Cameron McInally2014-06-161-0/+9
| | | | llvm-svn: 211024
* Add HasCDI predicate to AVX512 VPBROADCASTM*.Cameron McInally2014-06-131-0/+2
| | | | llvm-svn: 210892
* Add AVX512 masked leadz instrinsic support.Cameron McInally2014-06-111-0/+22
| | | | llvm-svn: 210652
* [X86] AVX512: Add vmovntdqaAdam Nemet2014-06-101-0/+11
| | | | | | Along with the corresponding intrinsic and tests. llvm-svn: 210543
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-121-0/+56
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* AVX-512: minor change in rndscale intrinsicElena Demikhovsky2014-05-041-2/+11
| | | | llvm-svn: 207937
* AVX-512: optimized a shuffle pattern to VINSERTI64x4.Elena Demikhovsky2014-04-291-0/+16
| | | | | | Added intrinsics for VPERMT2PS/PD/D/Q instructions. llvm-svn: 207513
* AVX-512: store and truncstore for i1 valuesElena Demikhovsky2014-04-221-0/+12
| | | | llvm-svn: 206897
* [AVX512] Implemented integer conversions up/down with masking.Robert Khasanov2014-04-221-20/+58
| | | | | | Added encoding tests. llvm-svn: 206884
* Rename X86insrtps to the proper instruction name.Filipe Cabecinhas2014-04-211-2/+2
| | | | | | | | | | | | | | | Summary: The INSERTPS pattern fragment was called insrtps (mising 'e'), which would make it harder to grep for the patterns related to this instruction. Renaming it to use the proper instruction name. Reviewers: nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3443 llvm-svn: 206779
* AVX-512: insert element to mask vector; store i1 dataElena Demikhovsky2014-04-091-0/+16
| | | | | | | Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors; Implemented "store" for i1 type llvm-svn: 205850
* AVX-512: Added fp_to_uint and uint_to_fp patterns.Elena Demikhovsky2014-04-081-0/+11
| | | | llvm-svn: 205754
* Test commit.Robert Khasanov2014-03-311-2/+2
| | | | llvm-svn: 205214
* AVX-512: Implemented masking for integer arithmetic & logic instructions.Elena Demikhovsky2014-03-271-92/+260
| | | | | | By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
* Fix AVX512 Gather and Scatter execution domains.Cameron McInally2014-03-261-7/+16
| | | | llvm-svn: 204804
* AVX-512: masked load/store + intrinsics for them.Elena Demikhovsky2014-03-131-121/+108
| | | | llvm-svn: 203790
* AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP ↵Elena Demikhovsky2014-03-061-15/+52
| | | | | | | | packed instructions, added encoding tests for them. By Robert Khazanov. llvm-svn: 203098
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-021-0/+5
| | | | llvm-svn: 202624
* AVX-512: Fixed encoding of VPCMPEQ and VPCMPGTElena Demikhovsky2014-02-241-4/+8
| | | | llvm-svn: 202015
* AVX-512: Fixed encoding of VPTESTMQElena Demikhovsky2014-02-231-8/+11
| | | | llvm-svn: 201980
* AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by ↵Elena Demikhovsky2014-02-201-3/+8
| | | | | | | | Nis Zinovy (zinovy.y.nis@intel.com) Fixed truncate i32 to i1; a test will be provided in the next commit. llvm-svn: 201757
* Fix AVX512 vector sqrt assembly strings.Cameron McInally2014-02-191-4/+4
| | | | llvm-svn: 201681
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-29/+29
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* AVX-512: implemented zext fron i1 to i16Elena Demikhovsky2014-02-171-1/+3
| | | | llvm-svn: 201502
* AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequenceElena Demikhovsky2014-02-161-5/+0
| | | | llvm-svn: 201487
* AVX-512: Optimized BUILD_VECTOR pattern; Elena Demikhovsky2014-02-111-1/+1
| | | | | | fixed encoding of VEXTRACTPS instruction. llvm-svn: 201134
* AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky2014-02-101-2/+2
| | | | llvm-svn: 201066
* AVX-512: Added intrinsic for cvtph2ps.Elena Demikhovsky2014-02-051-22/+60
| | | | | | | Added VPTESTNM instruction. Added a pattern to vselect (lit tests will follow). llvm-svn: 200823
* Simplify some x86 format classes and remove some ambiguities in their ↵Craig Topper2014-02-011-23/+26
| | | | | | application. llvm-svn: 200608
* Remove duplicate pattern and add predicate checks on other patterns.Craig Topper2014-01-301-1/+2
| | | | llvm-svn: 200455
* AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,Elena Demikhovsky2014-01-231-148/+156
| | | | | | they give better sequences than VPERMI llvm-svn: 199893
* AVX-512: optimized scalar compare patternsElena Demikhovsky2014-01-141-15/+15
| | | | | | removed AVX512SI format, since it is similar to AVX512BI. llvm-svn: 199217
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-40/+40
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-144/+197
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.Elena Demikhovsky2014-01-081-35/+70
| | | | llvm-svn: 198745
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-061-0/+8
| | | | llvm-svn: 198593
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-051-24/+26
| | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. llvm-svn: 198562
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-051-12/+38
| | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. llvm-svn: 198557
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-051-3/+3
| | | | | | disassembler without string matches. llvm-svn: 198545
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-1/+1
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-021-68/+88
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-55/+203
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512.Elena Demikhovsky2013-12-251-0/+4
| | | | llvm-svn: 198008
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-241-3/+10
| | | | llvm-svn: 197981
* AVX512: SETCC returns i1 for AVX-512 and i8 for all othersElena Demikhovsky2013-12-221-0/+2
| | | | llvm-svn: 197876
* AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey ↵Elena Demikhovsky2013-12-171-0/+7
| | | | | | | | Bader). Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1. llvm-svn: 197482
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-8/+85
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
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