| Commit message (Collapse) | Author | Age | Files | Lines |
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information and update all callers. No functional change.
llvm-svn: 214781
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Any CPU can run this pass.
llvm-svn: 213190
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llvm-svn: 210442
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we know next time this happens.
llvm-svn: 210127
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llvm-svn: 210126
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the pass pipeline.
llvm-svn: 209382
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llvm-svn: 209381
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According to Intel Software Optimization Manual on Silvermont in some cases LEA
is better to be replaced with ADD instructions:
"The rule of thumb for ADDs and LEAs is that it is justified to use LEA
with a valid index and/or displacement for non-destructive destination purposes
(especially useful for stack offset cases), or to use a SCALE.
Otherwise, ADD(s) are preferable."
Differential Revision: http://reviews.llvm.org/D3826
llvm-svn: 209198
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llvm-svn: 207197
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definition below all of the header #include lines, lib/Target/...
edition.
llvm-svn: 206842
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class.
llvm-svn: 203378
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llvm-svn: 191715
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on ADD16rr opcodes, if src1 != src, since that would cause
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.
This patch fixes PR16785.
llvm-svn: 191711
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the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183571
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Expunge all remaining traces and use of live variable information.
llvm-svn: 180577
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latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.
llvm-svn: 180573
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