summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86FastISel.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* X86FastISel support for loading and storing values of type i1.Dan Gohman2009-08-271-3/+15
| | | | llvm-svn: 80186
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-13/+14
| | | | llvm-svn: 78948
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-72/+72
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-100/+100
| | | | | | own struct type. llvm-svn: 78610
* Teach X86FastISel how to handle CCValAssign::BCvt, which is used forDan Gohman2009-08-051-0/+8
| | | | | | MMX arguments. This fixes PR4684. llvm-svn: 78163
* Move a few more APIs back to 2.5 forms. The only remaining ones left to ↵Owen Anderson2009-07-311-2/+2
| | | | | | | | change back are metadata related, which I'm waiting on to avoid conflicting with Devang. llvm-svn: 77721
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-2/+2
| | | | llvm-svn: 76702
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Begin the painful process of tearing apart the rat'ss nest that is ↵Owen Anderson2009-07-131-2/+2
| | | | | | | | | Constants.cpp and ConstantFold.cpp. This involves temporarily hard wiring some parts to use the global context. This isn't ideal, but it's the only way I could figure out to make this process vaguely incremental. llvm-svn: 75445
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* code model is never set to default.Chris Lattner2009-07-101-4/+2
| | | | llvm-svn: 75278
* remove the now-dead TM argument to these methods.Chris Lattner2009-07-101-2/+2
| | | | llvm-svn: 75276
* add a couple of predicates to test for "stub style pic in PIC mode" and ↵Chris Lattner2009-07-101-5/+3
| | | | | | "stub style pic in dynamic-no-pic" mode. llvm-svn: 75273
* simplify fast isel by using ClassifyGlobalReference. ThisChris Lattner2009-07-101-38/+14
| | | | | | elimiantes the last use of GVRequiresExtraLoad, so delete it. llvm-svn: 75244
* GVRequiresExtraLoad is now never used for calls, simplify it based on this.Chris Lattner2009-07-101-1/+1
| | | | llvm-svn: 75232
* actually, just eliminate PCRelGVRequiresExtraLoad. It makes the codeChris Lattner2009-07-101-2/+1
| | | | | | more complex and slow than just directly testing what we care about. llvm-svn: 75231
* There is only one case where GVRequiresExtraLoad returns true for calls:Chris Lattner2009-07-101-76/+14
| | | | | | | split its handling out to PCRelGVRequiresExtraLoad, and simplify code based on this. llvm-svn: 75230
* split call handling out of X86SelectAddress into X86SelectCallAddressChris Lattner2009-07-101-18/+164
| | | | llvm-svn: 75228
* Thread LLVMContext through MVT and related parts of SDISel.Owen Anderson2009-07-091-2/+2
| | | | llvm-svn: 75153
* move reasoning about darwin $non_lazy_ptr stubs from asmprinter intoChris Lattner2009-07-091-11/+35
| | | | | | isel. llvm-svn: 75117
* rearrange some code, no functionality change.Chris Lattner2009-07-091-23/+28
| | | | llvm-svn: 75113
* make direct calls set MO_PLT or MO_DARWIN_STUB as appropriate with fast isel.Chris Lattner2009-07-091-7/+36
| | | | llvm-svn: 75112
* simplify some code based on the fact that picstyles != none are only valid Chris Lattner2009-07-091-18/+13
| | | | | | in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot. llvm-svn: 75101
* @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.Chris Lattner2009-07-021-1/+3
| | | | | | This fixes an llvm-gcc bootstrap problem I introduced. llvm-svn: 74691
* Fix yet-another bug I introduced into fastisel, this time handlingChris Lattner2009-07-021-1/+3
| | | | | | constant pool references that weren't getting properly rip-relative. llvm-svn: 74689
* Fix a bunch of other places that used operator[] to test whetherDan Gohman2009-07-021-2/+3
| | | | | | a key is present in a std::map or DenseMap to use find instead. llvm-svn: 74676
* Fix some fast-isel problems selecting global variable addressing inChris Lattner2009-07-011-4/+14
| | | | | | pic mode. llvm-svn: 74582
* simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.Chris Lattner2009-06-271-5/+4
| | | | llvm-svn: 74377
* fix clang/test/CodeGenObjC/try.m, a basereg doesn't mean no global anymore.Chris Lattner2009-06-271-5/+3
| | | | llvm-svn: 74375
* Reimplement rip-relative addressing in the X86-64 backend. The newChris Lattner2009-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. llvm-svn: 74372
* Fix PR4466 by making fastisel set operand flags correctly.Chris Lattner2009-06-271-5/+12
| | | | llvm-svn: 74366
* Fix Bug 4278: X86-64 with -tailcallopt calling conventionArnold Schwaighofer2009-06-121-2/+0
| | | | | | | | | | | | | | | out of sync with regular cc. The only difference between the tail call cc and the normal cc was that one parameter register - R9 - was reserved for calling functions through a function pointer. After time the tail call cc has gotten out of sync with the regular cc. We can use R11 which is also caller saved but not used as parameter register for potential function pointers and remove the special tail call cc on x86-64. llvm-svn: 73233
* Avoid a warning "'U' might be used uninitialized inDuncan Sands2009-06-031-1/+1
| | | | | | this function" when using a not-too-smart compiler. llvm-svn: 72768
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-091-2/+2
| | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. llvm-svn: 71349
* X86FastISel doesn't support the -tailcallopt ABI.Dan Gohman2009-05-041-0/+6
| | | | llvm-svn: 70902
* Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman2009-04-271-2/+2
| | | | | | GR32_ABCD, and GR64_ABCD, respectively, to help describe them. llvm-svn: 70210
* Implement x86 h-register extract support.Dan Gohman2009-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
* fix a cross-block fastisel crash handling overflow intrinsics.Chris Lattner2009-04-121-5/+16
| | | | | | See comment for details. This fixes rdar://6772169 llvm-svn: 68890
* simplify code by using IntrinsicInst.Chris Lattner2009-04-121-69/+54
| | | | llvm-svn: 68887
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-15/+3
| | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. llvm-svn: 68886
* Re-apply 68552.Rafael Espindola2009-04-081-2/+2
| | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td llvm-svn: 68560
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-2/+2
| | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. llvm-svn: 68552
* Improve FastISel's handling of truncates to i1, and implementDan Gohman2009-03-131-0/+13
| | | | | | | | ptrtoint and inttoptr in X86FastISel. These casts aren't always handled in the generic FastISel code because X86 sometimes needs custom code to do truncation and zero-extension. llvm-svn: 66988
* Fix FastISel's assumption that i1 values are always zero-extendedDan Gohman2009-03-131-2/+4
| | | | | | | | | by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. llvm-svn: 66941
* generalize this code so that fast isel handles integer truncates to i1, whichChris Lattner2009-03-131-2/+4
| | | | | | | codegen to the same thing as integer truncates to i8 (the top bits are just undefined). This implements rdar://6667338 llvm-svn: 66902
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* do not export all the X86FastISel symbols, ever.Chris Lattner2009-03-081-1/+4
| | | | llvm-svn: 66382
* Fast-isel can't do TLS yet, so it should fall back to SDISelDan Gohman2009-02-231-0/+6
| | | | | | if it sees TLS addresses. llvm-svn: 65341
* Remove non-DebugLoc versions of BuildMI from X86.Dale Johannesen2009-02-131-38/+41
| | | | | | There were some that might even matter in X86FastISel. llvm-svn: 64437
OpenPOWER on IntegriCloud