summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86FastISel.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* [FastISel][X86] Use XOR to materialize the "0" value.Juergen Ributzka2014-08-131-0/+23
| | | | llvm-svn: 215594
* [FastISel][X86] Emit more efficient instructions for integer constant ↵Juergen Ributzka2014-08-131-1/+28
| | | | | | | | | | | | | materialization. This mostly affects the i64 value type, which always resulted in an 15byte mobavsq instruction to materialize any constant. The custom code checks the value of the immediate and tries to use a different and smaller mov instruction when possible. This fixes <rdar://problem/17420988>. llvm-svn: 215593
* [FastISel][X86] Refactor constant materialization. NFCI.Juergen Ributzka2014-08-131-54/+67
| | | | | | | Split the constant materialization code into three separate helper functions for Integer-, Floating-Point-, and GlobalValue-Constants. llvm-svn: 215586
* [FastISel][X86] Silence -Wenum-compare warningRui Ueyama2014-08-081-2/+6
| | | | llvm-svn: 215253
* [FastISel][X86] Fix INC/DEC optimization (r215230)Juergen Ributzka2014-08-081-1/+1
| | | | | | | | I accidentally also used INC/DEC for unsigned arithmetic which doesn't work, because INC/DEC don't set the required flag which is used for the overflow check. llvm-svn: 215237
* [FastISel][X86] Use INC/DEC when possible for {sadd|ssub}.with.overflow ↵Juergen Ributzka2014-08-081-5/+24
| | | | | | | | | | intrinsics. This is a small peephole optimization to emit INC/DEC when possible. Fixes <rdar://problem/17952308>. llvm-svn: 215230
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-5/+3
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-5/+5
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [X86] Simplify X87 stackifier pass.Akira Hatanaka2014-08-011-34/+28
| | | | | | | | | | | | | | | | | | | Stop using ST registers for function returns and inline-asm instructions and use FP registers instead. This allows removing a large amount of code in the stackifier pass that was needed to track register liveness and handle copies between ST and FP registers and function calls returning floating point values. It also fixes a bug which manifests when an ST register defined by an inline-asm instruction was live across another inline-asm instruction, as shown in the following sequence of machine instructions: 1. INLINEASM <es:frndint> $0:[regdef], %ST0<imp-def,tied5> 2. INLINEASM <es:fldcw $0> 3. %FP0<def> = COPY %ST0 <rdar://problem/16952634> llvm-svn: 214580
* [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during ↵Juergen Ributzka2014-07-311-0/+5
| | | | | | | | | | function call lowering. UNDEF arguments are not ment to be touched - especially for the webkit_js calling convention. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214366
* [FastISel] Move the helper function isCommutativeIntrinsic into FastISel ↵Juergen Ributzka2014-07-301-12/+0
| | | | | | | | | base class. Move the helper function isCommutativeIntrinsic into the FastISel base class, so it can be used by more than just one backend. llvm-svn: 214347
* Silence a warning in conditional expression.Andrea Di Biagio2014-07-151-1/+1
| | | | | | | | Fixes a gcc warning caused by a typo. A redundant assignment operation was accidentally used as the third operand of a conditional expression. No functional change intended. llvm-svn: 213061
* [FastISel][X86] Remove no longer needed functions.Juergen Ributzka2014-07-151-462/+0
| | | | llvm-svn: 213051
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-151-41/+41
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 213050
* [FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka2014-07-151-9/+400
| | | | | | | | | | | | This implements the FastLowerCall hook, which is based on the DoSelectCall function. The implementation is very similar, but the target-independent call lowering part has been factored out. This should also enable patchpoint intrinsic lowering for FastISel on X86. Related to <rdar://problem/17427052>. llvm-svn: 213049
* Revert "[FastISel][X86] Remove no longer needed functions."Juergen Ributzka2014-07-151-244/+315
| | | | | | | | | | Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook." Revert "[FastISel][X86] Implement the FastLowerCall hook." This reverts commit r213035, r213036, and r213037 to make the buildbots happy again. llvm-svn: 213048
* [FastISel][X86] Remove no longer needed functions.Juergen Ributzka2014-07-151-462/+0
| | | | llvm-svn: 213037
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-151-41/+41
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 213036
* [FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka2014-07-151-9/+400
| | | | | | | | | | | | This implements the FastLowerCall hook, which is based on the DoSelectCall function. The implementation is very similar, but the target-independent call lowering part has been factored out. This should also enable patchpoint intrinsic lowering for FastISel on X86. Related to <rdar://problem/17427052>. llvm-svn: 213035
* Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook."Juergen Ributzka2014-07-111-38/+42
| | | | | | This reverts commit r212851, because it broke the memset lowering. llvm-svn: 212855
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-111-42/+38
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 212851
* [FastISel][X86] Fix smul.with.overflow.i8 lowering.Juergen Ributzka2014-07-071-3/+19
| | | | | | | | | | | Add custom lowering code for signed multiply instruction selection, because the default FastISel instruction selection for ISD::MUL will use unsigned multiply for the i8 type and signed multiply for all other types. This would set the incorrect flags for the overflow check. This fixes <rdar://problem/17549300> llvm-svn: 212493
* X86: revert unintentional change to X86FastISel.Tim Northover2014-07-071-1/+1
| | | | | | This crept in with r212443. llvm-svn: 212459
* CodeGen: it turns out that NAND is not the same thing as BIC. At all.Tim Northover2014-07-071-1/+1
| | | | | | | | | | | We've been performing the wrong operation on ARM for "atomicrmw nand" for years, since "a NAND b" is "~(a & b)" rather than ARM's very tempting "a & ~b". This bled over into the generic expansion pass. So I assume no-one has ever actually tried to do an atomic nand in the real world. Oh well. llvm-svn: 212443
* X86: fix commentSaleem Abdulrasool2014-06-301-1/+1
| | | | | | Fix a comment typo `DbgLocLImport` instead of `DLLImport`. llvm-svn: 212012
* [FastISel][X86] Fix typos.Juergen Ributzka2014-06-271-13/+13
| | | | llvm-svn: 211911
* Rename getX86ConditonCode -> getX86ConditionCodeCraig Topper2014-06-271-5/+5
| | | | llvm-svn: 211869
* [FastISel][X86] More refactoring of select lowering and XALU folding. NFC.Juergen Ributzka2014-06-251-83/+55
| | | | llvm-svn: 211740
* [FastISel][X86] Refactor XALU folding. NFC.Juergen Ributzka2014-06-251-124/+70
| | | | llvm-svn: 211735
* [FastISel][X86] Only fold the cmp into the select when both instructions are ↵Juergen Ributzka2014-06-251-5/+15
| | | | | | | | | | | | in the same basic block. If the cmp is in a different basic block, then it is possible that not all operands of that compare have defined registers. This can happen when one of the operands to the cmp is a load and the load gets folded into the cmp. In this case FastISel will skip the load instruction and the vreg is never defined. llvm-svn: 211730
* Fix indentation.Juergen Ributzka2014-06-251-7/+7
| | | | llvm-svn: 211717
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-241-0/+150
| | | | | | | Optimize the codegen of select and branch instructions to directly use the EFLAGS from the {s|u}{add|sub|mul}.with.overflow intrinsics. llvm-svn: 211645
* [FastISel][X86] Lower unsupported selects to control-flow.Juergen Ributzka2014-06-231-0/+71
| | | | | | | | The extends the select lowering coverage by emiting pseudo cmov instructions. These insturction will be later on lowered to control-flow to simulate the select. llvm-svn: 211545
* [FastISel][X86] Add support for floating-point select.Juergen Ributzka2014-06-231-0/+128
| | | | | | | | | | This extends the select lowering to support floating-point selects. The lowering depends on SSE instructions and that the conditon comes from a floating-point compare. Under this conditions it is possible to emit an optimized instruction sequence that doesn't require any branches to simulate the select. llvm-svn: 211544
* [FastISel][X86] Optimize selects when the condition comes from a compare.Juergen Ributzka2014-06-231-35/+145
| | | | | | | Optimize the select instructions sequence to use the EFLAGS directly from a compare when possible. llvm-svn: 211543
* Fix typosAlp Toker2014-06-191-1/+1
| | | | llvm-svn: 211304
* Allow X86FastIsel to cope with 64 bit absolute relocationsLouis Gerbarg2014-06-171-10/+12
| | | | | | | | | | | | This patch is a follow up to r211040 & r211052. Rather than bailing out of fast isel this patch will generate an alternate instruction (movabsq) instead of the leaq. While this will always have enough room to handle the 64 bit displacment it is generally over kill for internal symbols (most displacements will be within 32 bits) but since we have no way of communicating the code model to the the assmebler in order to avoid flagging an absolute leal/leaq as illegal when using a symbolic displacement. llvm-svn: 211130
* [FastISel][X86] Optimize predicates and fold CMP instructions.Juergen Ributzka2014-06-171-13/+109
| | | | | | | | | This optimizes predicates for certain compares, such as fcmp oeq %x, %x to fcmp ord %x, %x. The latter one is more efficient to generate. The same optimization is applied to conditional branches. llvm-svn: 211126
* [FastISel][X86] Fix previous refactoring commit (r211077)Juergen Ributzka2014-06-171-4/+4
| | | | | | | Overlooked that fcmp_une uses an "or" instead of an "and" for combining the flags. llvm-svn: 211104
* [FastISel][X86] Refactor the code to get the X86 condition from a helper ↵Juergen Ributzka2014-06-161-92/+102
| | | | | | | | | function. NFC. Make use of helper functions to simplify the branch and compare instruction selection in FastISel. Also add test cases for compare and conditonal branch. llvm-svn: 211077
* Improve comments for r211040Louis Gerbarg2014-06-161-1/+4
| | | | | | | | Added comment to clarify why we r211040 choose to bail out of fast isel instead of generating a more complicated relocation, and fix mislabelled register in the comments of the asan test case. llvm-svn: 211052
* Fix illegal relocations in X86FastISelLouis Gerbarg2014-06-161-0/+4
| | | | | | | | | | | | On x86_86 the lea instruction can only use a 32 bit immediate value. When the code is compiled statically the RIP register is not used, meaning the immediate is all that can be used for the relocation, which is not sufficient in the case of targets more than +/- 2GB away. This patch bails out of fast isel in those cases and reverts to DAG which does the right thing. Test case included. llvm-svn: 211040
* [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.Juergen Ributzka2014-06-131-0/+66
| | | | | | | | This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding insertelement instructions are folded into the conversion instruction (if possible). llvm-svn: 210870
* [FastISel][X86] - Add branch weightsJuergen Ributzka2014-06-131-3/+16
| | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). llvm-svn: 210863
* [FastISel][X86] Add MachineMemOperand to load/store instructions.Juergen Ributzka2014-06-121-39/+68
| | | | | | | | This commit adds MachineMemOperands to load and store instructions. This allows the peephole optimizer to fold load instructions. Unfortunatelly the peephole optimizer currently doesn't run at -O0. llvm-svn: 210858
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-121-20/+41
| | | | | | | Recommit with fixed argument attribute checking code, which is required to bail out of all the cases we don't handle yet. llvm-svn: 210815
* Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point ↵Juergen Ributzka2014-06-121-36/+19
| | | | | | | | arguments." Reverting it because it breaks several tests. llvm-svn: 210810
* [FastISel][X86] Add support for the sqrt intrinsic.Juergen Ributzka2014-06-111-0/+52
| | | | llvm-svn: 210720
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-111-19/+36
| | | | llvm-svn: 210719
* [FastISel][X86] Add support for the frameaddress intrinsic.Juergen Ributzka2014-06-111-0/+52
| | | | llvm-svn: 210709
OpenPOWER on IntegriCloud