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* ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OSDaniel Dunbar2011-04-201-2/+2
| | | | | | triple component. llvm-svn: 129838
* Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar2011-04-191-1/+2
| | | | llvm-svn: 129813
* Add support for FastISel'ing varargs calls.Eli Friedman2011-04-191-4/+21
| | | | llvm-svn: 129765
* Implement support for x86 fastisel of small fixed-sized memcpys, which are ↵Chris Lattner2011-04-191-5/+50
| | | | | | | | | generated en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x and shrinks the generated .s file by 5% llvm-svn: 129755
* tidy upChris Lattner2011-04-191-3/+5
| | | | llvm-svn: 129753
* Implement support for fast isel of calls of i1 arguments, even though they ↵Chris Lattner2011-04-191-10/+23
| | | | | | | | | | | | are illegal, when they are a truncate from something else. This eliminates fully half of all the fastisel rejections on a test c++ file I'm working with, which should make a substantial improvement for -O0 compile of c++ code. This fixed rdar://9297003 - fast isel bails out on all functions taking bools llvm-svn: 129752
* Handle i1/i8/i16 constant integer arguments to calls by prepromoting them.Chris Lattner2011-04-191-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | Before we would bail out on i1 arguments all together, now we just bail on non-constant ones. Also, we used to emit extraneous code. e.g. test12 was: movb $0, %al movzbl %al, %edi callq _test12 and test13 was: movb $0, %al xorl %edi, %edi movb %al, 7(%rsp) callq _test13f Now we get: movl $0, %edi callq _test12 and: movl $0, %edi callq _test13f llvm-svn: 129751
* be layout aware, to produce:Chris Lattner2011-04-191-1/+8
| | | | | | | | | | | | | | | | | | | testb $1, %al je LBB0_2 ## BB#1: ## %if.then movb $0, %al instead of: testb $1, %al jne LBB0_1 jmp LBB0_2 LBB0_1: ## %if.then movb $0, %al how 'bout that. llvm-svn: 129749
* fix rdar://9297006 - fast isel bails out on trunc to i1 -> bools cry,Chris Lattner2011-04-191-6/+29
| | | | | | a common cause of fast isel rejects on c++ code. llvm-svn: 129748
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-22/+13
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* fix an x86 fast isel issue where we'd completely give up on folding an addressChris Lattner2011-04-171-71/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when we have a global variable base an an index. Instead, just give up on folding the global variable. Before we'd geenrate: _test: ## @test ## BB#0: movq _rtx_length@GOTPCREL(%rip), %rax leaq (%rax), %rax addq %rdi, %rax movzbl (%rax), %eax ret now we generate: _test: ## @test ## BB#0: movq _rtx_length@GOTPCREL(%rip), %rax movzbl (%rax,%rdi), %eax ret The difference is even more significant when there is a scale involved. This fixes rdar://9289558 - total fail with addr mode formation at -O0/x86-64 llvm-svn: 129664
* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-4/+7
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* tidy up and reduce indentation.Chris Lattner2011-04-171-37/+39
| | | | llvm-svn: 129661
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-111-0/+1
| | | | llvm-svn: 129271
* Fix fast-isel address mode folding to avoid folding instructionsDan Gohman2011-03-221-16/+22
| | | | | | outside of the current basic block. This fixes PR9500, rdar://9156159. llvm-svn: 128041
* Target/X86/X86FastISel: [PR6275] Fix Win32's dllimport function with fastisel.NAKAMURA Takumi2011-02-211-2/+6
| | | | | | | "dllimport" function must not be GlobalVariable, but Function. It is enough to check with GlobalValue. test/CodeGen/X86/dll-linkage.ll is updated to check llc -O0. llvm-svn: 126110
* reapply my fix for PR8961 with a tweak to properly handleChris Lattner2011-01-161-1/+1
| | | | | | | multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. llvm-svn: 123559
* revert my fastisel patch again which apparently still gives theChris Lattner2011-01-141-1/+1
| | | | | | llvm-gcc-i386-linux-selfhost buildbot heartburn... llvm-svn: 123431
* reapply r123414 now that the botz are calmed down and the fix is already in.Chris Lattner2011-01-141-1/+1
| | | | llvm-svn: 123427
* r123414 broke llvm-gcc bootstrap apparently, revertChris Lattner2011-01-141-1/+1
| | | | llvm-svn: 123422
* fix PR8961 - a fast isel miscompilation where we'd insert a new instructionChris Lattner2011-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret llvm-svn: 123414
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-2/+2
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Remove dead code and silence warnings.Benjamin Kramer2011-01-061-2/+0
| | | | llvm-svn: 122957
* silence more self assignment warnings.Chris Lattner2011-01-051-3/+3
| | | | llvm-svn: 122920
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-76/+76
| | | | llvm-svn: 119990
* Reapply r118917. With pseudo-instruction expansion moved toDan Gohman2010-11-161-5/+5
| | | | | | | a different pass, the complicated interaction between cmov expansion and fast isel is no longer a concern. llvm-svn: 119400
* Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.Dan Gohman2010-11-131-5/+5
| | | | llvm-svn: 118954
* When the definition of an address value is in a different blockDan Gohman2010-11-121-5/+5
| | | | | | | | from the user of the address, fall back to just using the address in a register instead of bailing out of fast-isel altogether. llvm-svn: 118917
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-1/+1
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-24/+25
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* Factorize the duplicated logic for choosing the right argumentDuncan Sands2010-10-311-28/+1
| | | | | | | calling convention out of the fast and normal ISel files, and into the calling convention TD file. llvm-svn: 117856
* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. llvm-svn: 117855
* Noticed by inspection when looking for other cmov bits.Eric Christopher2010-09-291-0/+3
| | | | llvm-svn: 115100
* MMX parameters aren't handled here yet.Dale Johannesen2010-09-271-0/+3
| | | | llvm-svn: 114844
* implement rdar://6653118 - fastisel should fold loads where possible.Chris Lattner2010-09-051-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since mem2reg isn't run at -O0, we get a ton of reloads from the stack, for example, before, this code: int foo(int x, int y, int z) { return x+y+z; } used to compile into: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx movl 4(%rsp), %esi addl %edx, %esi movl (%rsp), %edx addl %esi, %edx movl %edx, %eax addq $12, %rsp ret Now we produce: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx addl 4(%rsp), %edx ## Folded load addl (%rsp), %edx ## Folded load movl %edx, %eax addq $12, %rsp ret Fewer instructions and less register use = faster compiles. llvm-svn: 113102
* Fix x86 fast-isel's cmp+branch folding to avoid folding when theDan Gohman2010-08-211-2/+4
| | | | | | | | comparison is in a different basic block from the branch. In such cases, the comparison's operands may not have initialized virtual registers available. llvm-svn: 111709
* Make fast isel win64-aware w.r.t. call-clobbered regsNate Begeman2010-07-221-3/+14
| | | | llvm-svn: 109069
* Use MI.isCopy.Jakob Stoklund Olesen2010-07-161-4/+2
| | | | llvm-svn: 108565
* Last COPY conversion.Jakob Stoklund Olesen2010-07-141-3/+2
| | | | llvm-svn: 108387
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-1/+1
| | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. llvm-svn: 108302
* Don't fast-isel an x87 comparison opcode, as fast-isel doesn'tDan Gohman2010-07-121-2/+2
| | | | | | support branching on x87 comparisons yet. This fixes PR7624. llvm-svn: 108149
* Avoid SSE instructions in FastIsel when it is not available.Jakob Stoklund Olesen2010-07-111-4/+4
| | | | llvm-svn: 108091
* Use COPY in X86FastISel::X86SelectRet.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | | | | Don't try a cross-class copy. That is very unlikely anywy since return value registers are usually register class friendly. (%EAX, %XMM0, etc). llvm-svn: 108074
* Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen2010-07-111-18/+8
| | | | | | | The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. llvm-svn: 108069
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-60/+218
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-199/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-60/+199
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-2/+2
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-4/+3
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-187/+59
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
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