bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵	Ayman Musa	2017-03-07	1	-1/+7
\| \| \| \| \| \| \| \| \| \| \| \|	compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
*	[X86] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵	Eugene Zelenko	2017-02-02	1	-12/+20
\| \| \| \| \| \|	minor fixes (NFC). llvm-svn: 293949
*	This is a large patch for X86 AVX-512 of an optimization for reducing code ↵	Gadi Haber	2016-12-28	1	-0/+213
	size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663