summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86DomainReassignment.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [X86] Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-061-3/+3
|
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders2019-08-011-6/+6
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367633
* X86: Clean up pass initializationTom Stellard2019-06-131-3/+1
| | | | | | | | | | | | | | | | | | | | Summary: - Remove redundant initializations from pass constructors that were already being initialized by LLVMInitializeX86Target(). - Add initialization function for the FPS pass. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63218 llvm-svn: 363221
* [X86] In X86DomainReassignment.cpp add enclosed registers to EnclosedEdgesGuozhi Wei2019-03-051-0/+1
| | | | | | | | | | The variable X86DomainReassignment::EnclosedEdges is used to store registers that have been enclosed in some closure, so those registers will be ignored when create new closures. But there is no registers has ever been put into this set, so a single register can be enclosed in multiple closures, it significantly increase compile time. This patch adds a register into EnclosedEdges when it is enclosed into a closure. Differential Revision: https://reviews.llvm.org/D58646 llvm-svn: 355430
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [X86] Disable DomainReassignment pass when AVX512BW is disabled to avoid ↵Craig Topper2019-01-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | injecting VK32/VK64 references into the MachineIR Summary: This pass replaces GR8/GR16/GR32/GR64 with their equivalent sized mask register classes. But VK32/VK64 aren't legal without AVX512BW. Apparently this mostly appears to work if the register coalescer is able to remove the VK32/VK64 register class reference. Or if we don't ever spill it. But there's no guarantee of that. Another Intel employee managed to trigger a crash due to this with ISPC. Unfortunately, I've lost the test case he sent me at the time. I'm trying to get him to reproduce it for me. I'd like to get this in before 8.0 branches since its a little scary. The regressions here are unfortunate, but I think we can make some improvements to DAG combine, load folding, etc. to fix them. Just not sure if we can get that done for 8.0. Fixes PR39741 Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56460 llvm-svn: 350800
* X86: Consistently declare pass initializers in X86.h; NFCMatthias Braun2018-11-011-4/+0
| | | | | | | This avoids declaring them twice: in X86TargetMachine.cpp and the file implementing the pass. llvm-svn: 345801
* [X86] Stop X86DomainReassignment from creating copies between GR8/GR16 ↵Craig Topper2018-10-011-0/+21
| | | | | | | | | | | | | | physical registers and k-registers. We can only copy between a k-register and a GR32/GR64 register. This patch detects that the copy will be illegal and prevents the domain reassignment from happening for that closure. This probably isn't the best fix, and we should probably figure out how to handle this correctly. Fixes PR38803. llvm-svn: 343443
* Remove DEBUG macro.Nicola Zaghen2018-05-231-1/+1
| | | | | | | | | | Now that the LLVM_DEBUG() macro landed on the various sub-projects the DEBUG macro can be removed. Also change the new uses of DEBUG to LLVM_DEBUG. Differential Revision: https://reviews.llvm.org/D46952 llvm-svn: 333091
* [X86DomainReassignment] Don't compare stack-allocated values by addressKeno Fischer2018-05-181-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The Closure allocated in the main loop is allocated on the stack. However, later in the code its address is taken (and used for comparisons). This obviously doesn't work. In fact, the Closure will get the same stack address during every loop iteration, rendering the check that intended to identify Closure conflicts entirely ineffective. Fix this bug by giving every Closure a unique ID and using that for comparison. Alternatively, we could heap allocate the closure object. Fixes PR37396 Fixes JuliaLang/julia#27032 Reviewers: craig.topper, guyblank Reviewed By: craig.topper Subscribers: vchuravy, llvm-commits Differential Revision: https://reviews.llvm.org/D46800 llvm-svn: 332682
* [X86DomainReassignment] Don't delete IMPLICIT_DEF nodesKeno Fischer2018-05-181-20/+1
| | | | | | | | | | | | | | | | Summary: We cannot simply delete IMPLICIT_DEF nodes. They may be used later (e.g. by a PHI) and deleting them will cause later passes (e.g. LiveVariables) to crash. However, it seems fine to ignore them for purposes of the domain reassignment (as we do with PHI). Fixes PR37430 Fixes JuliaLang/julia#27080 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46797 llvm-svn: 332680
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+6
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* Clear converters map after X86 Domain Reassignment to avoid crashesDimitry Andric2018-05-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: As reported in PR37264, in some cases the X86 Domain Reassignment `runOnMachineFunction()` is called twice. Because it only deletes the `.second` members of its `InstrConverterBaseMap`, and does not clean up the map itself, this can lead to double frees and crashes. Use `DeleteContainerSeconds()` instead, so the `Converters` map can safely be reinitialized and its members re-deleted for each X86 Domain Reassignment pass. Reviewers: guyblank, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46425 llvm-svn: 332176
* [X86] Don't emit KTEST instructions unless only the Z flag is being usedCraig Topper2018-02-081-4/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: KTEST has weird flag behavior. The Z flag is set for all bits in the AND of the k-registers being 0, and the C flag is set for all bits being 1. All other flags are cleared. We currently emit this instruction in EmitTEST and don't check the condition code. This can lead to strange things like using the S flag after a KTEST for a signed compare. The domain reassignment pass can also transform TEST instructions into KTEST and is not protected against the flag usage either. For now I've disabled this part of the domain reassignment pass. I tried to comment out the checks in the mir test so that we could recover them later, but I couldn't figure out how to get that to work. This patch moves the KTEST handling into LowerSETCC and now creates a ktest+x86setcc. I've chosen this approach because I'd like to add support for the C flag for all ones in a followup patch. To do that requires that I can rewrite the condition code going in the x86setcc to be different than the original SETCC condition code. This fixes PR36182. I'll file a PR to fix domain reassignment once this goes in. Should this be merged to 6.0? Reviewers: spatel, guyblank, RKSimon, zvi Reviewed By: guyblank Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42770 llvm-svn: 324576
* [X86] Refactor DomainReassignment pass to make the Closure class not stores ↵Craig Topper2017-12-201-78/+89
| | | | | | | | | | | | references to the main data structures of the pass itself Multiple Closure objects can be created and stored for a single function. It's not a good idea to devote so many fields of it to storing pointers and references to global data structures of the pass. The closure class should only store the things needed to represent the closure itself. This patch refactors many of the methods of Closure to belong to the pass object and to pass around a reference to the current Closure. The Closure class gains a few simple methods to add instructions and edges, and to return iterators to edges and instructions Differential Revision: https://reviews.llvm.org/D41327 llvm-svn: 321213
* [X86DomainReassignment] Store legal domains in a std::bitset instead of ↵Craig Topper2017-12-171-16/+18
| | | | | | using a SmallVector that really only ever has one element as a set. llvm-svn: 320940
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-131-1/+0
| | | | llvm-svn: 320636
* [X86] Fix a bug in handling GRXX subclasses in Domain Reassignment passGuy Blank2017-12-051-4/+4
| | | | | | | | | | | When trying to determine the correct Mask register class corresponding to a GPR register class, not all register classes were handled. This caused an assertion to be raised on some scenarios. Differential Revision: https://reviews.llvm.org/D40290 llvm-svn: 319745
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Fix a -Wpedantic warning.Haojian Wu2017-10-231-1/+1
| | | | llvm-svn: 316315
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-221-0/+752
The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
OpenPOWER on IntegriCloud