| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix line endings. | Eli Friedman | 2017-01-30 | 1 | -208/+208 |
| | | | | | llvm-svn: 293554 | ||||
| * | [X86] Vectorcall Calling Convention - Adding CodeGen Complete Support | Oren Ben Simhon | 2016-12-21 | 1 | -4/+4 |
| | | | | | | | Fixing build issues. llvm-svn: 290244 | ||||
| * | [X86] Vectorcall Calling Convention - Adding CodeGen Complete Support | Oren Ben Simhon | 2016-12-21 | 1 | -3/+151 |
| | | | | | | | | | | | | | | The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible. vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use. The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above. The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it. This aubmit also includes additional lit tests to cover better HVAs corner cases. Differential Revision: https://reviews.llvm.org/D27392 llvm-svn: 290240 | ||||
| * | [X86] RegCall - Handling v64i1 in 32/64 bit target | Oren Ben Simhon | 2016-11-17 | 1 | -0/+60 |
| Register Calling Convention defines a new behavior for v64i1 types. This type should be saved in GPR. However for 32 bit machine we need to split the value into 2 GPRs (because each is 32 bit). Differential Revision: https://reviews.llvm.org/D26181 llvm-svn: 287217 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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