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path: root/llvm/lib/Target/X86/PeepholeOptimizer.cpp
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* Renamed files to have the `X86' prefix for uniqueness purposes.Misha Brukman2004-07-261-515/+0
| | | | | | All CVS history was renamed, the *,v were copied over. No worries. llvm-svn: 15238
* Convert to the new TargetMachine interface.Chris Lattner2004-06-021-1/+1
| | | | llvm-svn: 13952
* Add more ADC and SBB variantsAlkis Evlogimenos2004-04-021-4/+8
| | | | llvm-svn: 12607
* A big X86 instruction rename. The instructions are renamed to makeAlkis Evlogimenos2004-02-291-57/+57
| | | | | | | | | | | | | | | | their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory llvm-svn: 11995
* Uncomment instructions that take both an immediate and a memoryAlkis Evlogimenos2004-02-281-5/+0
| | | | | | operand but their sizes differ. llvm-svn: 11969
* Do not generate instructions with mismatched memory/immediate sizedAlkis Evlogimenos2004-02-281-1/+5
| | | | | | operands. The X86 backend doesn't handle them properly right now. llvm-svn: 11944
* Move MOTy::UseType enum into MachineOperand. This eliminates theAlkis Evlogimenos2004-02-221-1/+2
| | | | | | | | | switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). llvm-svn: 11715
* The two address pass cannot handle two addr instructions where one incomingChris Lattner2004-02-221-9/+16
| | | | | | | | value is a physreg and one is a virtreg. For this reason, disable copy folding entirely for physregs. Also, use the new isMoveInstr target hook which gives us folding of FP moves as well. llvm-svn: 11700
* Add OR and XOR memory operand support.Alkis Evlogimenos2004-02-171-0/+6
| | | | llvm-svn: 11549
* Peephole optimize SUBmi{16,32} into SUBmi{16,32}b when immediate is 8Alkis Evlogimenos2004-02-171-0/+3
| | | | | | bits wide. llvm-svn: 11548
* ADDmi{16,32} should be in the next case statement.Alkis Evlogimenos2004-02-171-3/+3
| | | | llvm-svn: 11547
* Disable this peephole for now. We can't keep track of the fact that the ↵Chris Lattner2004-02-171-0/+2
| | | | | | | | immediate is 8 bits, but the memory reference is full sized. llvm-svn: 11536
* Fix the mneumonics for the mov instructions to have the source and destinationChris Lattner2004-02-171-4/+4
| | | | | | order in the correct sense!! Arg! llvm-svn: 11530
* Fix the last crimes against nature that used the 'ir' ordering to use theChris Lattner2004-02-171-2/+2
| | | | | | | 'ri' ordering instead... no it's not possible to store a register into an immediate! llvm-svn: 11529
* Rename MOVi[mr] instructions to MOV[rm]iChris Lattner2004-02-171-8/+8
| | | | llvm-svn: 11527
* Whoops, got my cases swapped.Chris Lattner2004-02-171-6/+6
| | | | llvm-svn: 11526
* Add mem forms of AND instructionsChris Lattner2004-02-171-2/+27
| | | | llvm-svn: 11521
* Rename the IMULri* instructions to IMULrri, as they are actually three addressChris Lattner2004-02-171-3/+28
| | | | | | instructions. Add forms of these instructions that read from memory llvm-svn: 11518
* Add peephole optimizations for ADD [MEM], IMM8 instructions.Alkis Evlogimenos2004-02-161-0/+3
| | | | llvm-svn: 11511
* Make dense maps keyed on physical registers smallerusingAlkis Evlogimenos2004-02-151-1/+1
| | | | | | | | | | MRegisterInfo::getNumRegs() instead of MRegisterInfo::FirstVirtualRegister. Also use MRegisterInfo::is{Physical,Virtual}Register where appropriate. llvm-svn: 11477
* Use newly added next() and prior() utility functions.Alkis Evlogimenos2004-02-141-2/+4
| | | | llvm-svn: 11430
* Change MachineBasicBlock's vector of MachineInstr pointers into anAlkis Evlogimenos2004-02-121-17/+18
| | | | | | | | | ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. llvm-svn: 11340
* Add #includeChris Lattner2004-02-101-0/+1
| | | | llvm-svn: 11285
* Remove uses of MachineOperand::isVirtualRegisterChris Lattner2004-02-101-3/+6
| | | | llvm-svn: 11281
* Modify the two address instruction pass to remove the duplicateAlkis Evlogimenos2004-02-041-8/+25
| | | | | | operand of the instruction and thus simplify the register allocation. llvm-svn: 11124
* Change interface of MachineOperand as follows:Alkis Evlogimenos2003-12-141-2/+2
| | | | | | | | | | | | | | | a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse() b) add isUse(), isDef() c) rename opHiBits32() to isHiBits32(), opLoBits32() to isLoBits32(), opHiBits64() to isHiBits64(), opLoBits64() to isLoBits64(). This results to much more readable code, for example compare "op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used very often in the code. llvm-svn: 10461
* Add a new SSA-based peephole optimizer which includes copy propagation andChris Lattner2003-12-011-2/+283
| | | | | | | | folding of instructions into addressing modes. This creates lots of dead instructions, which are currently not deleted. It also creates a lot of instructions that the X86 backend currently cannot handle. :( llvm-svn: 10275
* Finegrainify namespacificationChris Lattner2003-11-301-4/+2
| | | | llvm-svn: 10270
* Put all LLVM code into the llvm namespace, as per bug 109.Brian Gaeke2003-11-111-0/+4
| | | | llvm-svn: 9903
* Added LLVM project notice to the top of every C++ source file.John Criswell2003-10-201-0/+7
| | | | | | Header files will be on the way. llvm-svn: 9298
* Emit x86 instructions for: A = B op C, where A and B are 16-bit registers,Chris Lattner2003-10-201-0/+40
| | | | | | | | | | | | | | | | | | | | | | C is a constant which can be sign-extended from 8 bits without value loss, and op is one of: add, sub, imul, and, or, xor. This allows the JIT to emit the one byte version of the constant instead of the two or 4 byte version. Because these instructions are very common, this can save a LOT of code space. For example, I sampled two benchmarks, 176.gcc and 254.gap. BM Old New Reduction 176.gcc 2673621 2548962 4.89% 254.gap 498261 475104 4.87% Note that while the percentage is not spectacular, this did eliminate 124.6 _KILOBYTES_ of codespace from gcc. Not bad. Note that this doesn't effect the llc version at all, because the assembler already does this optimization. llvm-svn: 9284
* Factory methods for FunctionPasses now return type FunctionPass *.Brian Gaeke2003-08-131-1/+1
| | | | llvm-svn: 7823
* Fix problem with invalidated iteratorChris Lattner2003-01-161-1/+1
| | | | llvm-svn: 5327
* New filesChris Lattner2003-01-131-0/+86
llvm-svn: 5260
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