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path: root/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
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* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-2/+2
| | | | llvm-svn: 223339
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Move X86RegisterInfo away from using the TargetMachine and onlyEric Christopher2014-06-101-1/+2
| | | | | | using the subtarget. llvm-svn: 210595
* MC: create X86WinCOFFStreamer for target specific behaviourSaleem Abdulrasool2014-04-271-0/+9
| | | | | | | | | | This introduces a target specific streamer, X86WinCOFFStreamer, which handles the target specific behaviour (e.g. WinEH). This is mostly to ensure that differences between ARM and X86 remain disjoint and do not accidentally cross boundaries. This is the final staging change for enabling object emission for Windows on ARM. llvm-svn: 207344
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-091-2/+4
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* Enable ELF machine type to be specified explicitly in X86 backendMichael Liao2012-10-301-2/+3
| | | | llvm-svn: 167027
* Add register encoding support in X86 backendMichael Liao2012-10-041-2/+0
| | | | | | | | - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. llvm-svn: 165241
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-181-2/+2
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-151-0/+1
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Move x86 specific bits of the COFF writer to lib/Target/X86.Rafael Espindola2011-12-241-0/+2
| | | | llvm-svn: 147231
* Move the X86 specific bits of the ELF writer to the Target/X86 directory.Rafael Espindola2011-12-211-0/+4
| | | | | | Other targets will follow shortly. llvm-svn: 147060
* Add X86 feature detection support for BMI instructions. Added new cpuid ↵Craig Topper2011-10-161-0/+5
| | | | | | function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. llvm-svn: 142089
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-3/+3
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Unbreak the build.Oscar Fuentes2011-07-251-0/+1
| | | | llvm-svn: 135949
* More refactoring.Evan Cheng2011-07-251-0/+11
| | | | llvm-svn: 135939
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-251-0/+8
| | | | llvm-svn: 135930
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-1/+24
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-0/+3
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-0/+9
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-071-0/+14
| | | | llvm-svn: 134641
* Rename files for consistency.Evan Cheng2011-07-061-0/+34
llvm-svn: 134546
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