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path: root/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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* Add X86 feature detection support for BMI instructions. Added new cpuid ↵Craig Topper2011-10-161-0/+68
| | | | | | function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. llvm-svn: 142089
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-1/+2
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-2/+9
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng2011-08-231-0/+12
| | | | | | from MC. llvm-svn: 138367
* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-261-9/+9
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-8/+8
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-251-0/+18
| | | | llvm-svn: 135974
* More refactoring.Evan Cheng2011-07-251-0/+36
| | | | llvm-svn: 135939
* createXXXMCCodeGenInfo should be static.Evan Cheng2011-07-231-2/+2
| | | | llvm-svn: 135826
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-221-29/+23
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-2/+10
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-0/+47
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-6/+24
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-3/+140
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-3/+3
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-13/+36
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-6/+8
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Revert earlier unnecessary hack. Make sure we correctly force on 64bit and ↵Eli Friedman2011-07-081-1/+1
| | | | | | cmov for 64-bit targets. llvm-svn: 134768
* Default 64-bit target features and SSE2 on when a triple specifies x86-64. ↵Eli Friedman2011-07-081-27/+1
| | | | | | Clean up all the other hacks which are now unnecessary. llvm-svn: 134753
* For non-x86 host, used generic as CPU name.Evan Cheng2011-07-081-1/+6
| | | | llvm-svn: 134741
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-26/+17
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-071-1/+117
| | | | llvm-svn: 134641
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+3
| | | | llvm-svn: 134606
* Rename files for consistency.Evan Cheng2011-07-061-0/+74
llvm-svn: 134546
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