bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Add X86 RORX instruction	Craig Topper	2011-10-23	1	-0/+9
\| \| \| \|	llvm-svn: 142741
*	Add X86 PEXTR and PDEP instructions.	Craig Topper	2011-10-16	1	-3/+12
\| \| \| \|	llvm-svn: 142141
*	Add X86 BZHI instruction as well as BMI2 feature detection.	Craig Topper	2011-10-16	1	-29/+13
\| \| \| \|	llvm-svn: 142122
*	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵	Craig Topper	2011-10-16	1	-5/+26
\| \| \| \| \| \|	3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
*	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵	Craig Topper	2011-10-15	1	-14/+18
\| \| \| \| \| \|	because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
*	Tidy up a bit more, fix tab and remove trailing whitespaces	Bruno Cardoso Lopes	2011-09-20	1	-9/+5
\| \| \| \|	llvm-svn: 140186
*	Tidy up code!	Bruno Cardoso Lopes	2011-09-20	1	-6/+5
\| \| \| \|	llvm-svn: 140183
*	Re-write part of VEX encoding logic, to be more easy to read! Also fix	Bruno Cardoso Lopes	2011-08-19	1	-58/+82
\| \| \| \| \| \|	a bug and add a testcase! llvm-svn: 138123
*	Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the	Bruno Cardoso Lopes	2011-08-19	1	-3/+8
\| \| \| \| \| \|	implementation! llvm-svn: 138029
*	Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.	Evan Cheng	2011-07-27	1	-5/+0
\| \| \| \| \| \| \| \| \|	This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
*	Explicitly cast narrowing conversions inside {}s that will become errors in	Jeffrey Yasskin	2011-07-27	1	-1/+1
\| \| \| \| \| \|	C++0x. llvm-svn: 136211
*	More refactoring.	Evan Cheng	2011-07-25	1	-0/+1055
	llvm-svn: 135939