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* [X86] Avoid mangling frameescape labelsReid Kleckner2015-04-291-1/+5
| | | | | | | | | | | | | | x86 Windows uses the '_' prefix for all global symbols, and this was mistakenly being applied to frameescape labels, which are not externally visible global symbols. They use the private global prefix 'L'. The *right* way to fix this is probably to stop masquerading this label as an ExternalSymbol and create a new SDNode type. These labels are not "external", and we know they will be resolved by assembly time. Having a custom SDNode type would allow us to do better X86 address mode matching, so it's probably worth doing eventually. llvm-svn: 236123
* [X86] Add the remaining 11 possible exact ModRM formats. This makes their ↵Craig Topper2015-02-151-13/+15
| | | | | | encodings linear which can then be used to simplify some other code. llvm-svn: 229279
* [X86] Simplify code a little by just summing flags instead of conditionally ↵Craig Topper2015-01-051-18/+7
| | | | | | incrementing. NFC llvm-svn: 225156
* [X86] Remove unnecessary redeclaration of a variable with the same ↵Craig Topper2015-01-051-1/+0
| | | | | | assignment as the beginning of the function. NFC. llvm-svn: 225155
* [X86] Remove a strange fixme referring to a hack that doesn't seem to exist ↵Craig Topper2015-01-051-3/+0
| | | | | | since the code is in a comment. Can't figure out what the body of the 'if' was supposed to be anyway. llvm-svn: 225154
* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-8/+15
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-1/+1
| | | | llvm-svn: 223339
* Use uint64_t as the type for the X86 TSFlag format enum. Allows removal of ↵Craig Topper2014-11-111-30/+36
| | | | | | the VEXShift hack that was used to access the higher bits of TSFlags. llvm-svn: 221673
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-25/+27
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [X86] AVX512: Use the TD version of CD8_Scale in the assemblerAdam Nemet2014-07-171-8/+4
| | | | | | | | | | | Passes the computed scaling factor in TSFlags rather than the old attributes. Also removes the C++ version of computing the scaling factor (MemObjSize) along with the asserts added by the previous patch. No functional change. llvm-svn: 213279
* [X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet2014-07-141-3/+6
| | | | | | | | | | | | | | | No functional change. The offsets for the other bitfields are specified symbolically. I need to increase the size for one of the earlier fields which is easier after this cleanup. Why these bits are relative to VEXShift is a bit strange but that is for another cleanup. I made sure that the values for the enums are unchanged after this change. llvm-svn: 213011
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-121-3/+6
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* Prune includes in X86 target.Craig Topper2014-03-191-1/+1
| | | | llvm-svn: 204216
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-21/+29
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Reduce size of map field in X86 TSFlags since it now requires less bits.Craig Topper2014-02-191-2/+2
| | | | llvm-svn: 201646
* Put some of the X86 formats in a more logical order.Craig Topper2014-02-191-16/+16
| | | | llvm-svn: 201645
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-19/+16
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-6/+6
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-0/+6
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-6/+0
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-0/+6
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-6/+9
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-27/+33
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-38/+34
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-10/+10
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-3/+24
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+6
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+5
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+5
| | | | llvm-svn: 199803
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-0/+5
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-0/+10
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-1/+3
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-061-8/+1
| | | | llvm-svn: 198588
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-061-3/+5
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-311-7/+0
| | | | llvm-svn: 198257
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+3
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-11/+68
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-11/+13
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd2013-04-101-1/+21
| | | | | | | | | | | | into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. llvm-svn: 179211
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-13/+10
| | | | llvm-svn: 177888
* Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg2013-01-291-2/+2
| | | | llvm-svn: 173798
* Add support of RTM from TSX extensionMichael Liao2012-11-081-8/+8
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Remove 'static' from inline functions defined in header files.Chandler Carruth2012-06-201-7/+7
| | | | | | | | | | | | | | | | | There is a pretty staggering amount of this in LLVM's header files, this is not all of the instances I'm afraid. These include all of the functions that (in my build) are used by a non-static inline (or external) function. Specifically, these issues were caught by the new '-Winternal-linkage-in-inline' warning. I'll try to just clean up the remainder of the clearly redundant "static inline" cases on functions (not methods!) defined within headers if I can do so in a reliable way. There were even several cases of a missing 'inline' altogether, or my personal favorite "static bool inline". Go figure. ;] llvm-svn: 158800
* Better comments for TLS-related X86 MachineOperand flags.Hans Wennborg2012-06-041-9/+18
| | | | llvm-svn: 157920
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-0/+27
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-111-0/+7
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ↵Pete Cooper2012-04-301-1/+3
| | | | | | emitter. Needs some major refactoring as these two code emitters are almost identical llvm-svn: 155810
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-6/+8
| | | | llvm-svn: 150899
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