bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Add X86 assembler and disassembler support for AMD SVM instructions. ↵	Craig Topper	2012-02-18	1	-25/+16
\| \| \| \| \| \|	Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
*	Add support for implicit TLS model used with MS VC runtime.	Anton Korobeynikov	2012-02-11	1	-1/+7
\| \| \| \| \| \|	Patch by Kai Nacke! llvm-svn: 150307
*	Convert assert(0) to llvm_unreachable in X86 Target directory.	Craig Topper	2012-02-05	1	-5/+5
\| \| \| \|	llvm-svn: 149809
*	Separate the concept of having memory access in operand 4 from the concept ↵	Craig Topper	2011-12-30	1	-6/+5
\| \| \| \| \| \|	of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. llvm-svn: 147366
*	XOP encoding bits and logic.	Jan Sjödin	2011-12-12	1	-1/+11
\| \| \| \|	llvm-svn: 146397
*	This patch contains support for encoding FMA4 instructions and	Bruno Cardoso Lopes	2011-11-25	1	-1/+9
\| \| \| \| \| \| \| \| \|	tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin llvm-svn: 145133
*	Add X86 RORX instruction	Craig Topper	2011-10-23	1	-0/+3
\| \| \| \|	llvm-svn: 142741
*	Add X86 PEXTR and PDEP instructions.	Craig Topper	2011-10-16	1	-2/+5
\| \| \| \|	llvm-svn: 142141
*	Add X86 BZHI instruction as well as BMI2 feature detection.	Craig Topper	2011-10-16	1	-8/+9
\| \| \| \|	llvm-svn: 142122
*	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵	Craig Topper	2011-10-16	1	-2/+5
\| \| \| \| \| \|	3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
*	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵	Craig Topper	2011-10-15	1	-2/+7
\| \| \| \| \| \|	because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
*	Add support in the disassembler for ignoring the L-bit on certain VEX ↵	Craig Topper	2011-10-04	1	-1/+5
\| \| \| \| \| \|	instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
*	Refactor X86 target to separate MC code from Target code.	Evan Cheng	2011-07-25	1	-0/+544
	llvm-svn: 135930