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* [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when ↵Konstantin Belochapka2017-09-251-0/+1
| | | | | | | | | x86-asm-syntax=intel (PR34617). Fix for incorrect code generation when x86-asm-syntax=intel. Differential Revision: https://reviews.llvm.org/D37945 llvm-svn: 314140
* [X86][SSE4A] Generalized EXTRQI/INSERTQI shuffle decodesSimon Pilgrim2017-07-041-2/+2
| | | | | | The existing decodes only worked for v16i8 vectors, this adds support for any 128-bit vector llvm-svn: 307095
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-063-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-05-311-0/+4
| | | | llvm-svn: 304332
* This patch closes PR#32216: Better testing of schedule model instruction ↵Andrew V. Tischenko2017-04-141-2/+0
| | | | | | | | latencies/throughputs. The details are here: https://reviews.llvm.org/D30941 llvm-svn: 300311
* [X86] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-064-14/+21
| | | | | | This is preparation to reduce MCExpr.h dependencies.(vlsj-clangbuild)[622] llvm-svn: 294246
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-181-0/+11
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* This is a large patch for X86 AVX-512 of an optimization for reducing code ↵Gadi Haber2016-12-281-0/+5
| | | | | | | | | | | | size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
* [X86] Remove alternate CodeGenOnly version of (v)movq that declared the load ↵Craig Topper2016-11-221-3/+0
| | | | | | | | | | size as i128mem. Change all uses to the use the i64mem version. I'm sure this caused the load size to misprint in Intel syntax output. We were also inconsistent about which patterns used which instruction between VEX and EVEX. There are two different reg/reg versions of movq, one from a GPR and one from the lower 64-bits of an XMM register. This changes the loading folding table to use the single i64mem memory form for folding both cases. But we need to use TB_NO_REVERSE to prevent a duplicate entry in the unfolding table. llvm-svn: 287622
* [X86] Remove duplicate instructions for (v)movq and replace with patterns on ↵Craig Topper2016-11-211-2/+0
| | | | | | other instructions. NFC llvm-svn: 287519
* [X86] Add support for printing shuffle comments for VALIGN instructions.Craig Topper2016-10-221-0/+44
| | | | llvm-svn: 284915
* [X86][AVX512] Add mask/maskz writemask support to subvector broadcast ↵Simon Pilgrim2016-10-211-0/+40
| | | | | | shuffle decode comments llvm-svn: 284821
* X86: Allow expressions to appear as u8imm operands.Peter Collingbourne2016-10-202-0/+6
| | | | llvm-svn: 284688
* [AVX-512] Add shuffle comments for vbroadcast instructions.Craig Topper2016-10-151-0/+43
| | | | llvm-svn: 284305
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-41/+77
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* [X86] Rename VINSERTzrr to use a capital Z to match other instructions. NFCCraig Topper2016-07-191-2/+2
| | | | llvm-svn: 275939
* [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments supportSimon Pilgrim2016-07-141-0/+6
| | | | llvm-svn: 275400
* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-031-0/+16
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-031-17/+20
| | | | llvm-svn: 274468
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment ↵Simon Pilgrim2016-06-111-35/+17
| | | | | | | | generation Now matches other shuffles llvm-svn: 272464
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-101-1/+9
| | | | llvm-svn: 272371
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-101-30/+46
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction commentsSimon Pilgrim2016-06-091-0/+12
| | | | llvm-svn: 272319
* [AVX512] Fix shuffle decode printing for several instructions with write ↵Craig Topper2016-06-091-3/+3
| | | | | | masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
* [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR ↵Craig Topper2016-06-091-6/+2
| | | | | | instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. llvm-svn: 272249
* [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and ↵Craig Topper2016-06-031-29/+17
| | | | | | PSHUFLW. llvm-svn: 271628
* [x86] avoid printing unnecessary sign bits of hex immediates in asm comments ↵Sanjay Patel2016-05-281-4/+13
| | | | | | | | | | | (PR20347) It would be better to check the valid/expected size of the immediate operand, but this is generally better than what we print right now. Differential Revision: http://reviews.llvm.org/D20385 llvm-svn: 271114
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-211-0/+4
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* clean up; NFCISanjay Patel2016-05-181-5/+4
| | | | llvm-svn: 269962
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-111-2/+2
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.Simon Pilgrim2016-05-111-49/+49
| | | | llvm-svn: 269209
* [X86][AVX512] Updated shuffle comments instruction macros to split writemask ↵Simon Pilgrim2016-05-111-40/+46
| | | | | | | | instructions. NFC This will make it easier to support the different writemask cases in shuffle comments llvm-svn: 269174
* [X86][SSE] Added TODO comment to add support for AVX512 mask registers to ↵Simon Pilgrim2016-05-091-0/+1
| | | | | | | | shuffle comments This came up in discussion on D19198 llvm-svn: 268915
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [X86][SSE] Added support for MOVHPD/MOVLPD + MOVHPS/MOVLPS shuffle decoding.Simon Pilgrim2016-02-071-0/+32
| | | | llvm-svn: 260034
* [X86][AVX512] Added support for VPMOVZX shuffle decoding.Simon Pilgrim2016-02-061-75/+35
| | | | llvm-svn: 260007
* [X86][SSE] Moved shuffle decode CASE macros earlier. NFC.Simon Pilgrim2016-02-061-48/+48
| | | | | | To allow the helper functions to make use of them. llvm-svn: 259997
* [X86][SSE] Refactored PMOVZX shuffle decoding to use scalar input typesSimon Pilgrim2016-02-061-70/+44
| | | | | | | | First step towards being able to decode AVX512 PMOVZX instructions without a massive bloat in the shuffle decode switch statement. This should also make it easier to decode X86ISD::VZEXT target shuffles in the future. llvm-svn: 259995
* [X86][AVX512] Add support for AVX512 VMOVQ (load) shuffle decodingSimon Pilgrim2016-02-021-0/+1
| | | | llvm-svn: 259496
* [X86][AVX512] Add support for AVX512 VMOVD (load) shuffle decodingSimon Pilgrim2016-02-011-0/+1
| | | | llvm-svn: 259430
* [X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decodingSimon Pilgrim2016-02-011-0/+4
| | | | llvm-svn: 259427
* [X86][AVX512] Add support for AVX512 VINSERTPS shuffle decodingSimon Pilgrim2016-02-011-0/+2
| | | | llvm-svn: 259420
* Remove autoconf supportChris Bieneman2016-01-261-15/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* [X86] Remove a return after llvm_unreachable.Craig Topper2015-12-311-1/+0
| | | | llvm-svn: 256681
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