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* Remove trailing spaceFangrui Song2018-07-301-1/+1
| | | | | | sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338293
* [X86] NFC Refactor some code in InstPrintersGabor Buella2018-06-057-261/+199
| | | | | | | | | | | | | | Summary: Bringing some come duplicated in the AT&T and the Intel printers into a common parent class. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47682 llvm-svn: 334005
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-011-1/+0
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* [X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem in Intel syntax.Craig Topper2018-04-261-1/+1
| | | | | | This matches objdump. llvm-svn: 330922
* [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print ↵Craig Topper2018-04-222-5/+9
| | | | | | | | | | 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. Improve the error messages to match GNU assembler. This also allows us to remove the hack from the disassembler table building. llvm-svn: 330531
* [X86] Don't pass getRegisterName from the InstPrinters into ↵Craig Topper2018-03-294-13/+13
| | | | | | | | EmitAnyX86InstComments. Just always use the function from the ATTPrinter. NFC The IntelPrinter and the ATTPrinter produce the same strings for the same input. We already use the ATTPrinter explicitly in several other places. llvm-svn: 328762
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-172-0/+6
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* [X86] Remove use of MVT class from the ShuffleDecode library.Craig Topper2018-03-121-105/+87
| | | | | | | | MVT belongs to the CodeGen layer, but ShuffleDecode is used by the X86 InstPrinter which is part of the MC layer. This only worked because MVT is completely implemented in a header file with no other library dependencies. Differential Revision: https://reviews.llvm.org/D44353 llvm-svn: 327292
* [X86] Add comments to the end of FMA3 instructions to make the operation clearCraig Topper2018-03-101-0/+286
| | | | | | | | | | | | | | | | | | | | | Summary: There are 3 different operand orders for FMA instructions so figuring out the exact operation being performed requires a lot of thought. This patch adds a comment to the end of the assembly line to print the exact operation. I think I've got all the instructions in here except the ones with builtin rounding. I didn't update all tests, but I assume we can get them as we regenerate tests in the future. Reviewers: spatel, v_klochkov, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44345 llvm-svn: 327225
* [X86] Add a missing EVEX instruction to EmitAnyX86InstComments.Craig Topper2018-03-101-0/+1
| | | | | | The equivalent SSE and VEX instruction are already there. llvm-svn: 327205
* [X86] Move the AC_EVEX_2_VEX AsmComments enum to X86InstrInfo.h from ↵Craig Topper2018-03-101-7/+0
| | | | | | | | | | X86InstComments.h. X86InstComments.h is used by tools that only have the MC layer. We shouldn't be importing a file from CodeGen into this. X86InstrInfo.h isn't a great place, but I couldn't find a better one. llvm-svn: 327202
* [X86] Rewrite printMasking code in X86InstComments to use TSFlags to ↵Craig Topper2018-03-104-189/+20
| | | | | | | | determine whether the instruction is masked. This should have been NFC, but it looks like we were missing PUNPCKLHQDQ/PUNPCKLQDQ instructions in there. llvm-svn: 327200
* [X86] Teach Intel syntax InstPrinter to print lock prefixes that have been ↵Craig Topper2018-01-251-2/+2
| | | | | | | | parsed from the asm parser. The asm parser puts the lock prefix in the MCInst flags so we need to check that in addition to TSFlags. This matches what the ATT printer does. llvm-svn: 323469
* [X86] Combine two unnecessarily complicated ifs that had the same body. NFCCraig Topper2018-01-251-3/+1
| | | | llvm-svn: 323468
* Any Target Asm comments should start from MachineInstr::TAsmComments value.Andrew V. Tischenko2017-12-141-1/+4
| | | | llvm-svn: 320693
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-101-4/+4
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own.Andrew V. Tischenko2017-11-032-6/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D39546 llvm-svn: 317330
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-162-0/+14
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [X86] Remove temporary std::string creation from shuffle comment printing. ↵Craig Topper2017-10-111-12/+12
| | | | | | We can just write directly to the raw_ostream. llvm-svn: 315399
* [X86] Add 128-bit version of vbroadcasti32x2 to shuffle comment decoding.Craig Topper2017-10-111-0/+11
| | | | llvm-svn: 315395
* [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when ↵Konstantin Belochapka2017-09-251-0/+1
| | | | | | | | | x86-asm-syntax=intel (PR34617). Fix for incorrect code generation when x86-asm-syntax=intel. Differential Revision: https://reviews.llvm.org/D37945 llvm-svn: 314140
* [X86][SSE4A] Generalized EXTRQI/INSERTQI shuffle decodesSimon Pilgrim2017-07-041-2/+2
| | | | | | The existing decodes only worked for v16i8 vectors, this adds support for any 128-bit vector llvm-svn: 307095
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-063-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-05-311-0/+4
| | | | llvm-svn: 304332
* This patch closes PR#32216: Better testing of schedule model instruction ↵Andrew V. Tischenko2017-04-141-2/+0
| | | | | | | | latencies/throughputs. The details are here: https://reviews.llvm.org/D30941 llvm-svn: 300311
* [X86] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-064-14/+21
| | | | | | This is preparation to reduce MCExpr.h dependencies.(vlsj-clangbuild)[622] llvm-svn: 294246
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-181-0/+11
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* This is a large patch for X86 AVX-512 of an optimization for reducing code ↵Gadi Haber2016-12-281-0/+5
| | | | | | | | | | | | size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
* [X86] Remove alternate CodeGenOnly version of (v)movq that declared the load ↵Craig Topper2016-11-221-3/+0
| | | | | | | | | | size as i128mem. Change all uses to the use the i64mem version. I'm sure this caused the load size to misprint in Intel syntax output. We were also inconsistent about which patterns used which instruction between VEX and EVEX. There are two different reg/reg versions of movq, one from a GPR and one from the lower 64-bits of an XMM register. This changes the loading folding table to use the single i64mem memory form for folding both cases. But we need to use TB_NO_REVERSE to prevent a duplicate entry in the unfolding table. llvm-svn: 287622
* [X86] Remove duplicate instructions for (v)movq and replace with patterns on ↵Craig Topper2016-11-211-2/+0
| | | | | | other instructions. NFC llvm-svn: 287519
* [X86] Add support for printing shuffle comments for VALIGN instructions.Craig Topper2016-10-221-0/+44
| | | | llvm-svn: 284915
* [X86][AVX512] Add mask/maskz writemask support to subvector broadcast ↵Simon Pilgrim2016-10-211-0/+40
| | | | | | shuffle decode comments llvm-svn: 284821
* X86: Allow expressions to appear as u8imm operands.Peter Collingbourne2016-10-202-0/+6
| | | | llvm-svn: 284688
* [AVX-512] Add shuffle comments for vbroadcast instructions.Craig Topper2016-10-151-0/+43
| | | | llvm-svn: 284305
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-41/+77
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* [X86] Rename VINSERTzrr to use a capital Z to match other instructions. NFCCraig Topper2016-07-191-2/+2
| | | | llvm-svn: 275939
* [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments supportSimon Pilgrim2016-07-141-0/+6
| | | | llvm-svn: 275400
* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-031-0/+16
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-031-17/+20
| | | | llvm-svn: 274468
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment ↵Simon Pilgrim2016-06-111-35/+17
| | | | | | | | generation Now matches other shuffles llvm-svn: 272464
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-101-1/+9
| | | | llvm-svn: 272371
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-101-30/+46
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction commentsSimon Pilgrim2016-06-091-0/+12
| | | | llvm-svn: 272319
* [AVX512] Fix shuffle decode printing for several instructions with write ↵Craig Topper2016-06-091-3/+3
| | | | | | masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
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