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* [X86][SSE] Merged BLEND shuffle decode comments. NFC.Simon Pilgrim2015-11-161-48/+8
| | | | | | Now that we can recognise different vector sizes. llvm-svn: 253268
* [X86][SSE] Merged ALIGNR/SLLDQ/SRLDQ shuffle decode comments. NFC.Simon Pilgrim2015-11-161-30/+4
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253266
* [X86][SSE] Merged SHUF/PERM shuffle decode comments. NFC.Simon Pilgrim2015-11-161-79/+14
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253260
* [X86][SSE] Merged UNPCK shuffle decode comments. NFC.Simon Pilgrim2015-11-161-193/+75
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253258
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-161-61/+65
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* Revert r253160.Igor Breger2015-11-151-65/+61
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-151-61/+65
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( ↵Igor Breger2015-10-151-1/+64
| | | | | | | | shuffle packed values at 128-bit granularity ) Differential Revision: http://reviews.llvm.org/D13648 llvm-svn: 250400
* [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.Simon Pilgrim2015-09-131-0/+61
| | | | | | | Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles. Added shuffle decodes for 3DNow! PSWAPD shuffles. llvm-svn: 247526
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-061-0/+23
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* Reformat.NAKAMURA Takumi2015-05-251-65/+64
| | | | llvm-svn: 238126
* Prune CRLFs.NAKAMURA Takumi2015-05-251-982/+982
| | | | llvm-svn: 238125
* [X86][SSE] Shuffle mask decode support for zero extend, scalar float/double ↵Simon Pilgrim2015-01-311-0/+172
| | | | | | | | | | | | moves and integer load instructions This patch adds shuffle mask decodes for integer zero extends (pmovzx** and movq xmm,xmm) and scalar float/double loads/moves (movss/movsd). Also adds shuffle mask decodes for integer loads (movd/movq). Differential Revision: http://reviews.llvm.org/D7228 llvm-svn: 227688
* Line endings fix. NFC.Simon Pilgrim2015-01-281-786/+786
| | | | llvm-svn: 227374
* [X86][SSE] movddup shuffle mask decodesSimon Pilgrim2015-01-211-6/+24
| | | | | | Patch to provide shuffle decodes and asm comments for the SSE3/AVX1 movddup double duplication instructions. llvm-svn: 226705
* [AVX512] Add pretty-printing of shuffle mask for unpacksAdam Nemet2015-01-131-0/+64
| | | | llvm-svn: 225837
* [X86] Also pretty-print shuffle mask for INSERTPS rm variants.Ahmed Bougacha2014-12-151-3/+7
| | | | llvm-svn: 224260
* [X86][SSE] pslldq/psrldq shuffle mask decodesSimon Pilgrim2014-10-141-0/+38
| | | | | | | | Patch to provide shuffle decodes and asm comments for the sse pslldq/psrldq SSE2/AVX2 byte shift instructions. Differential Revision: http://reviews.llvm.org/D5598 llvm-svn: 219738
* [x86] Implement v16i16 support with AVX2 in the new vector shuffleChandler Carruth2014-09-251-0/+11
| | | | | | | | | | | | | | | lowering. This also implements the fancy blend lowering for v16i16 using AVX2 and teaches the X86 backend to print shuffle masks for 256-bit PSHUFB and PBLENDW instructions. It also makes the mask decoding correct for PBLENDW instructions. The yaks, they are legion. Tests are updated accordingly. There are some missing tests for the VBLENDVB lowering, but I'll add those in a follow-up as this commit has accumulated enough cruft already. llvm-svn: 218430
* [x86] Teach the rest of the 'target shuffle' machinery about blends andChandler Carruth2014-09-231-0/+24
| | | | | | | | | | | add VPBLENDD to the InstPrinter's comment generation so we get nice comments everywhere. Now that we have the nice comments, I can see the bug introduced by a silly typo in the commit that enabled VPBLENDD, and have fixed it. Yay tests that are easy to inspect. llvm-svn: 218335
* [x86] Teach the vector comment parsing and printing to correctly handleChandler Carruth2014-09-231-3/+5
| | | | | | | | | | | | | | | | | undef in the shuffle mask. This shows up when we're printing comments during lowering and we still have an IR-level constant hanging around that models undef. A nice consequence of this is *much* prettier test cases where the undef lanes actually show up as undef rather than as a particular set of values. This also allows us to print shuffle comments in cases that use undef such as the recently added variable VPERMILPS lowering. Now those test cases have nice shuffle comments attached with their details. The shuffle lowering for PSHUFB has been augmented to use undef, and the shuffle combining has been augmented to comprehend it. llvm-svn: 218301
* [x86] Teach the x86 DAG combiner to form MOVSLDUP and MOVSHDUPChandler Carruth2014-09-151-0/+36
| | | | | | | | | | | | instructions when it finds an appropriate pattern. These are lovely instructions, and its a shame to not use them. =] They are fast, and can hand loads folded into their operands, etc. I've also plumbed the comment shuffle decoding through the various layers so that the test cases are printed nicely. llvm-svn: 217758
* [x86] Teach the asm comment printing to only print the clarification ofChandler Carruth2014-09-031-43/+50
| | | | | | | | | | an immediate operand when we don't have instruction-specific comments. This ensures that instruction-specific comments are attached to the same line as the instruction which is important for using them to write readable and maintainable tests. My next commit will just such a test. llvm-svn: 217099
* [x86] Teach the instruction printer to decode immediate operands toChandler Carruth2014-08-151-0/+64
| | | | | | | | | BLENDPS, BLENDPD, and PBLENDW instructions into pretty shuffle comments. These will be used in my next commit as part of test cases for AVX shuffles which can directly use blend in more places. llvm-svn: 215701
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* Replace ValueTypes.h with MachineValueType.h if possible.Patrik Hagglund2014-03-151-1/+1
| | | | | | | | | Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
* Replace '#include ValueTypes.h' with forward declarations.Patrik Hagglund2014-03-121-0/+2
| | | | | | | In some cases the include is pushed "downstream" (or removed if unused). llvm-svn: 203644
* To allow the X86 verbose assembly to print its informative commentsKevin Enderby2014-01-211-44/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when used with symbolic disassembly, add a check that the operand is an immediate and has not been symbolicated to MCExpr operand. I’m trying to enable the ‘C’ disassembly API option LLVMDisassembler_Option_SetInstrComments for darwin’s otool(1) that uses the llvm disassembler API. The problem is that the disassembler API can change an immediate operand to an MCExpr operand if it symbolicates it with the call backs. And if it does the code in llvm::EmitAnyX86InstComments() will crash when it assumes these operands are immediates. The fix for this is very straight forward to just protect the call to getImm() with a check of isImm(). So if the immediate for an instruction is symbolicated it simply doesn’t get the X86 verbose assembly comments: % otool -tV test_asm.o test_asm.o: (__TEXT,__text) section _t1: 0000000000000000 vpshufd $_t1, %xmm1, %xmm0 0000000000000005 retq 0000000000000006 nopw %cs:_t1(%rax,%rax) _t2: 0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3] 0000000000000015 retq 0000000000000016 nopw %cs:_t1(%rax,%rax) _t3: 0000000000000020 vpshufd $_t1, %xmm1, %xmm0 0000000000000025 retq 0000000000000026 nopw %cs:_t1(%rax,%rax) _t4: 0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0] 0000000000000035 retq The fact that the immediate $0x0 is being symbolicated at all in this case is a different problem which my next patch will address. rdar://10989286 llvm-svn: 199697
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-98/+14
| | | | llvm-svn: 173777
* Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper2013-01-281-0/+1
| | | | | | because the comment itself is still wrong. llvm-svn: 173669
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-281-6/+6
| | | | | | instruction. llvm-svn: 173667
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-261-0/+22
| | | | llvm-svn: 173572
* Add shuffle decode support for VPERMQ/VPERMPD.Craig Topper2012-05-061-0/+10
| | | | llvm-svn: 156265
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-021-2/+22
| | | | | | for AsmPrinter. llvm-svn: 155982
* Use a signed value for this enum to avoid spuriuos warnings from gcc.Benjamin Kramer2012-03-211-1/+1
| | | | llvm-svn: 153184
* Factor out target shuffle mask decoding from getShuffleScalarElt and use a ↵Craig Topper2012-03-201-5/+5
| | | | | | SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. llvm-svn: 153079
* Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd ↵Craig Topper2012-02-061-9/+20
| | | | | | decoding. llvm-svn: 149859
* Clean up some of the shuffle decoding code for UNPCK instructions. Add ↵Craig Topper2011-12-061-20/+148
| | | | | | instruction commenting for AVX/AVX2 forms for integer UNPCKs. llvm-svn: 145924
* Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node ↵Craig Topper2011-11-301-8/+8
| | | | | | type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. llvm-svn: 145483
* Fix shuffle decoding for memory forms for (V)SHUFPS/D.Craig Topper2011-11-291-6/+12
| | | | llvm-svn: 145392
* Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle ↵Craig Topper2011-11-291-14/+48
| | | | | | decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. llvm-svn: 145390
* More fixes to the X86InstComments for shuffle instructions. In particular ↵Craig Topper2011-11-221-12/+60
| | | | | | add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. llvm-svn: 145063
* Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors ↵Craig Topper2011-11-221-2/+30
| | | | | | correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. llvm-svn: 145055
* Add memory version of SHUFPD to mask decoding!Bruno Cardoso Lopes2011-08-251-1/+3
| | | | llvm-svn: 138545
* The VPERM2F128 is a AVX instruction which permutes between two 256-bitBruno Cardoso Lopes2011-08-121-0/+5
| | | | | | | | vectors. It operates on 128-bit elements instead of regular scalar types. Recognize shuffles that are suitable for VPERM2F128 and teach the x86 legalizer how to handle them. llvm-svn: 137519
* Add obviously missing "break". Noticed by Andrey Karpov withDuncan Sands2011-08-041-0/+1
| | | | | | the PVS-studio tool. llvm-svn: 136878
* Add DecodeShuffle shuffle support for VPERMIPD variantesBruno Cardoso Lopes2011-07-291-1/+10
| | | | llvm-svn: 136452
* Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng2011-07-261-1/+1
| | | | | | MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. llvm-svn: 136027
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 llvm-svn: 135662
* Rename files for consistency.Evan Cheng2011-07-061-1/+1
| | | | llvm-svn: 134546
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