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path: root/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
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* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-031-0/+16
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-031-17/+20
| | | | llvm-svn: 274468
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment ↵Simon Pilgrim2016-06-111-35/+17
| | | | | | | | generation Now matches other shuffles llvm-svn: 272464
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-101-1/+9
| | | | llvm-svn: 272371
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-101-30/+46
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction commentsSimon Pilgrim2016-06-091-0/+12
| | | | llvm-svn: 272319
* [AVX512] Fix shuffle decode printing for several instructions with write ↵Craig Topper2016-06-091-3/+3
| | | | | | masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
* [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR ↵Craig Topper2016-06-091-6/+2
| | | | | | instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. llvm-svn: 272249
* [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and ↵Craig Topper2016-06-031-29/+17
| | | | | | PSHUFLW. llvm-svn: 271628
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-211-0/+4
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-111-2/+2
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.Simon Pilgrim2016-05-111-49/+49
| | | | llvm-svn: 269209
* [X86][AVX512] Updated shuffle comments instruction macros to split writemask ↵Simon Pilgrim2016-05-111-40/+46
| | | | | | | | instructions. NFC This will make it easier to support the different writemask cases in shuffle comments llvm-svn: 269174
* [X86][SSE] Added TODO comment to add support for AVX512 mask registers to ↵Simon Pilgrim2016-05-091-0/+1
| | | | | | | | shuffle comments This came up in discussion on D19198 llvm-svn: 268915
* [X86][SSE] Added support for MOVHPD/MOVLPD + MOVHPS/MOVLPS shuffle decoding.Simon Pilgrim2016-02-071-0/+32
| | | | llvm-svn: 260034
* [X86][AVX512] Added support for VPMOVZX shuffle decoding.Simon Pilgrim2016-02-061-75/+35
| | | | llvm-svn: 260007
* [X86][SSE] Moved shuffle decode CASE macros earlier. NFC.Simon Pilgrim2016-02-061-48/+48
| | | | | | To allow the helper functions to make use of them. llvm-svn: 259997
* [X86][SSE] Refactored PMOVZX shuffle decoding to use scalar input typesSimon Pilgrim2016-02-061-70/+44
| | | | | | | | First step towards being able to decode AVX512 PMOVZX instructions without a massive bloat in the shuffle decode switch statement. This should also make it easier to decode X86ISD::VZEXT target shuffles in the future. llvm-svn: 259995
* [X86][AVX512] Add support for AVX512 VMOVQ (load) shuffle decodingSimon Pilgrim2016-02-021-0/+1
| | | | llvm-svn: 259496
* [X86][AVX512] Add support for AVX512 VMOVD (load) shuffle decodingSimon Pilgrim2016-02-011-0/+1
| | | | llvm-svn: 259430
* [X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decodingSimon Pilgrim2016-02-011-0/+4
| | | | llvm-svn: 259427
* [X86][AVX512] Add support for AVX512 VINSERTPS shuffle decodingSimon Pilgrim2016-02-011-0/+2
| | | | llvm-svn: 259420
* [X86] Remove a return after llvm_unreachable.Craig Topper2015-12-311-1/+0
| | | | llvm-svn: 256681
* Fix line endingsSimon Pilgrim2015-12-131-14/+14
| | | | llvm-svn: 255459
* [X86][AVX512] Added support for VMOVQ shuffle commentsSimon Pilgrim2015-12-121-12/+14
| | | | llvm-svn: 255442
* [X86][AVX512] Added AVX512 VMOVLHPS/VMOVHLPS shuffle decode comments.Simon Pilgrim2015-11-211-0/+3
| | | | llvm-svn: 253777
* AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP ↵Igor Breger2015-11-191-22/+8
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14702 llvm-svn: 253548
* [X86][AVX512] Added AVX512 SHUFP*/VPERMILP* shuffle decode comments.Simon Pilgrim2015-11-171-20/+23
| | | | llvm-svn: 253396
* [X86][AVX512] Added support for AVX512 UNPCK shuffle decode comments.Simon Pilgrim2015-11-171-88/+32
| | | | llvm-svn: 253391
* [X86][SSE] Merged BLEND shuffle decode comments. NFC.Simon Pilgrim2015-11-161-48/+8
| | | | | | Now that we can recognise different vector sizes. llvm-svn: 253268
* [X86][SSE] Merged ALIGNR/SLLDQ/SRLDQ shuffle decode comments. NFC.Simon Pilgrim2015-11-161-30/+4
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253266
* [X86][SSE] Merged SHUF/PERM shuffle decode comments. NFC.Simon Pilgrim2015-11-161-79/+14
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253260
* [X86][SSE] Merged UNPCK shuffle decode comments. NFC.Simon Pilgrim2015-11-161-193/+75
| | | | | | Now that we can recognise different vector sizes - will make future AVX512 additions easier. llvm-svn: 253258
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-161-61/+65
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* Revert r253160.Igor Breger2015-11-151-65/+61
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-151-61/+65
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( ↵Igor Breger2015-10-151-1/+64
| | | | | | | | shuffle packed values at 128-bit granularity ) Differential Revision: http://reviews.llvm.org/D13648 llvm-svn: 250400
* [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.Simon Pilgrim2015-09-131-0/+61
| | | | | | | Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles. Added shuffle decodes for 3DNow! PSWAPD shuffles. llvm-svn: 247526
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-061-0/+23
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* Reformat.NAKAMURA Takumi2015-05-251-65/+64
| | | | llvm-svn: 238126
* Prune CRLFs.NAKAMURA Takumi2015-05-251-982/+982
| | | | llvm-svn: 238125
* [X86][SSE] Shuffle mask decode support for zero extend, scalar float/double ↵Simon Pilgrim2015-01-311-0/+172
| | | | | | | | | | | | moves and integer load instructions This patch adds shuffle mask decodes for integer zero extends (pmovzx** and movq xmm,xmm) and scalar float/double loads/moves (movss/movsd). Also adds shuffle mask decodes for integer loads (movd/movq). Differential Revision: http://reviews.llvm.org/D7228 llvm-svn: 227688
* Line endings fix. NFC.Simon Pilgrim2015-01-281-786/+786
| | | | llvm-svn: 227374
* [X86][SSE] movddup shuffle mask decodesSimon Pilgrim2015-01-211-6/+24
| | | | | | Patch to provide shuffle decodes and asm comments for the SSE3/AVX1 movddup double duplication instructions. llvm-svn: 226705
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