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* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-223-1/+32
| | | | llvm-svn: 199803
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-2/+0
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* [x86] Fix 16-bit disassembly of JCXZ/JECXZDavid Woodhouse2014-01-201-0/+19
| | | | llvm-svn: 199653
* [x86] Fix 16-bit handling of OpSize bitDavid Woodhouse2014-01-201-3/+5
| | | | | | | | | | When disassembling in 16-bit mode the meaning of the OpSize bit is inverted. Instructions found in the IC_OPSIZE context will actually *not* have the 0x66 prefix, and instructions in the IC context will have the 0x66 prefix. Make use of the existing special-case handling for the 0x66 prefix being in the wrong place, to cope with this. llvm-svn: 199650
* [x86] Infer disassembler mode from SubtargetInfo feature bitsDavid Woodhouse2014-01-202-16/+24
| | | | | | | | | | | | Aside from cleaning up the code, this also adds support for the -code16 environment and actually enables the MODE_16BIT mode that was previously not accessible. There is no point adding any testing for 16-bit yet though; basically nothing will work because we aren't handling the OpSize prefix correctly for 16-bit mode. llvm-svn: 199649
* VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions ↵Craig Topper2014-01-171-11/+0
| | | | | | don't use the size fields it controls. llvm-svn: 199470
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-11/+18
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-0/+2
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-3/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* X86Disassembler.cpp: Prune stray @return on translateFPRegister(). ↵NAKAMURA Takumi2014-01-011-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 198279
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-014-52/+10
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-013-12/+6
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-312-1/+5
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove old comment referring to an argument that no longer exists.Craig Topper2013-12-311-2/+0
| | | | llvm-svn: 198263
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-302-5/+1
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-254-122/+314
| | | | llvm-svn: 198013
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+1
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi2013-12-111-1/+1
| | | | llvm-svn: 196988
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi2013-11-281-2/+0
| | | | | | I forgot to commit them. They were staging in my local repo. llvm-svn: 195924
* X86 Disassembler: remove unused bool typedef-nameDavid Majnemer2013-11-051-2/+0
| | | | llvm-svn: 194062
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-1/+49
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Replace C++ style comment with a C style comment to satisfy some of the ↵Craig Topper2013-10-031-1/+1
| | | | | | build bots. llvm-svn: 191880
* Remove comma from the end of an enum.Craig Topper2013-10-031-1/+1
| | | | llvm-svn: 191877
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-033-39/+174
| | | | llvm-svn: 191874
* Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
| | | | llvm-svn: 191732
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-012-20/+0
| | | | llvm-svn: 191731
* Various x86 disassembler fixes.Craig Topper2013-09-302-40/+4
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Build fixRichard Mitton2013-08-301-1/+1
| | | | llvm-svn: 189699
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-7/+9
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-17/+12
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Remove trailing whitespace.Craig Topper2013-08-241-1/+1
| | | | llvm-svn: 189178
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-284-4/+181
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-203-0/+32
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-97/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-192-10/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Fix typoJoerg Sonnenberger2012-10-291-2/+2
| | | | llvm-svn: 166945
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-053-13/+13
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-311-0/+2
| | | | llvm-svn: 162999
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-1/+1
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-015-14/+18
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove ↵Craig Topper2012-07-311-5/+4
| | | | | | trailing whitespace. llvm-svn: 161029
* Tidy up trailing whitespaceCraig Topper2012-07-311-33/+33
| | | | llvm-svn: 161027
* Tidy up trailing whitespaceCraig Topper2012-07-311-12/+12
| | | | llvm-svn: 161026
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