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* Put global classes into the appropriate namespace.Benjamin Kramer2015-10-281-0/+2
| | | | | | | Most of the cases belong into an anonymous namespace. No functionality change intended. llvm-svn: 251515
* [X86] Rip out orphaned method declarations and other dead code. NFC.Benjamin Kramer2015-10-151-2/+0
| | | | llvm-svn: 250406
* [X86] NFC: Clean up and clang-format a few linesVedant Kumar2015-08-281-5/+5
| | | | llvm-svn: 246340
* [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassemblyVedant Kumar2015-08-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for disassembling unusual instruction sequences in 64-bit mode w.r.t the CALL rel16 instruction. It might be desirable to move the check somewhere else, but it essentially mimics the special case handling with JCXZ in 16-bit mode. The current behavior accepts the opcode size prefix and causes the call's immediate to stop disassembling after 2 bytes. When debugging sequences of instructions with this pattern, the disassembler output becomes extremely unreliable and essentially useless (if you jump midway into what lldb thinks is a unified instruction, you'll lose %rip). So we ignore the prefix and consume all 4 bytes when disassembling a 64-bit mode binary. Note: in Vol. 2A 3-99 the Intel spec states that CALL rel16 is N.S. N.S. is defined as: Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. (Vol. 2A 3-7) Since 0x66 is an operand override prefix we should be OK (although we may want to warn about 0x67 prefixes to 0xe8). On the CPUs I tested with, they all ignore the 0x66 prefix in 64-bit mode. Patch by Matthew Barney! Differential Revision: http://reviews.llvm.org/D9573 llvm-svn: 246038
* Explicitly clear the MI operand list when getInstruction() is called. Call ↵Cameron Esfahani2015-08-111-0/+1
| | | | | | | | | | | | | | MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler. Summary: Explicitly clear the MI operand list when getInstruction() is called. Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11665 llvm-svn: 244557
* [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.Douglas Katzman2015-06-261-1/+7
| | | | | | | | Patch by Matthew Barney. Thanks! Differential Revision: http://reviews.llvm.org/D9514 llvm-svn: 240795
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-092-0/+4
| | | | | | Added encoding tests. llvm-svn: 239403
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-10/+9
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-9/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-33/+33
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-9/+10
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-10/+9
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-9/+10
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-10/+9
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Refactor: Simplify boolean expressions in x86 targetDavid Blaikie2015-03-231-5/+2
| | | | | | | | | | Simplify boolean expressions with `true` and `false` with `clang-tidy` Patch by Richard Thomson. Differential Revision: http://reviews.llvm.org/D8519 llvm-svn: 233002
* [X86] Remove some unused code from disassembler.Craig Topper2015-03-031-12/+0
| | | | llvm-svn: 231055
* [X86] There are only 8 mask registers. Fail disassembly if instruction tries ↵Craig Topper2015-03-021-0/+2
| | | | | | to reference more. llvm-svn: 230931
* [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that ↵Craig Topper2015-03-021-20/+22
| | | | | | doesn't fit in 5-bits. Fixes PR22743. llvm-svn: 230924
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-9/+10
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-10/+9
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-131-8/+24
| | | | | | VPCOM instructions. llvm-svn: 229078
* [X86] Teach disassembler to handle illegal immediates on AVX512 integer ↵Craig Topper2015-01-282-0/+130
| | | | | | compare instructions. llvm-svn: 227302
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-212-14/+3
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-073-18/+1
| | | | llvm-svn: 225343
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-031-0/+2
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-312-6/+35
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* [x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler.Craig Topper2014-12-311-16/+5
| | | | llvm-svn: 225035
* [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble ↵Craig Topper2014-12-262-3/+9
| | | | | | references to them. llvm-svn: 224862
* [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. ↵Craig Topper2014-12-262-6/+9
| | | | | | Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-262-6/+48
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-38/+38
| | | | llvm-svn: 223339
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-122-9/+21
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-102-44/+28
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit ↵Craig Topper2014-10-071-0/+47
| | | | | | | | | | mode for certain instructions it shouldn't. Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present. Fixes PR21169. llvm-svn: 219194
* Formatting fixes. Most putting 'else' on the same line as the preceding ↵Craig Topper2014-10-071-38/+19
| | | | | | curly brace. llvm-svn: 219193
* Fix filename in header and use C++ version of the C header files.Craig Topper2014-10-071-5/+5
| | | | llvm-svn: 219192
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-133-6/+6
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [X86] Increase X86_MAX_OPERANDS from 5 to 6Adam Nemet2014-08-051-1/+1
| | | | | | | | | | | | | | | | | | | This controls the number of operands in the disassembler's x86OperandSets table. The entries describe how the operand is encoded and its type. Not to surprisingly 5 operands is insufficient for AVX512. Consider VALIGNDrrik in the next patch. These are its operand specifiers: { /* 328 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM512 }, { ENCODING_WRITEMASK, TYPE_VK8 }, { ENCODING_VVVV, TYPE_XMM512 }, { ENCODING_RM_CD64, TYPE_XMM512 }, { ENCODING_IB, TYPE_IMM8 }, }, llvm-svn: 214889
* Finish inverting the MC -> Object dependency.Rafael Espindola2014-07-231-1/+1
| | | | | | | There were still some disassembler bits in lib/MC, but their use of Object was only visible in the includes they used, not in the symbols. llvm-svn: 213808
* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-1/+5
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-173-3/+21
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-241-1/+2
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> llvm-svn: 211565
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-284-17/+15
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* [C++] Use 'nullptr'.Craig Topper2014-04-281-2/+2
| | | | llvm-svn: 207394
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-231-1/+1
| | | | llvm-svn: 206953
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-5/+5
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
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