|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | Luis Felipe Strano Moraes!
llvm-svn: 129558 | 
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| | instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644 | 
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| | X86 instruction decode structure was being interpreted as
being in units of bits, although it is actually stored in
units of bytes.
llvm-svn: 126147 | 
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| | llvm-svn: 117206 | 
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| | and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
llvm-svn: 103196 | 
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| | return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.
llvm-svn: 100229 | 
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| | static inline functions with macros.
llvm-svn: 91973 | 
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| | with symbols in AuroraUX's global namespace.
llvm-svn: 91879 | 
|  | incarnations), integrated into the MC framework.  
The disassembler is table-driven, using a custom TableGen backend to 
generate hierarchical tables optimized for fast decode.  The disassembler 
consumes MemoryObjects and produces arrays of MCInsts, adhering to the 
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets.  Please let me know if you encounter any problems
with it.
llvm-svn: 91749 |