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* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-311-0/+4
| | | | | | | | | | Support Intel AVX512 VP2INTERSECT instructions in llvm Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62366 llvm-svn: 362188
* [X86] Remove if that's always trueCraig Topper2019-04-301-2/+1
| | | | | | | | It's been like this since it was added in a refactor of this code. Fixes PR41659 llvm-svn: 359597
* [X86] Merge the different Jcc instructions for each condition code into ↵Craig Topper2019-04-051-1/+1
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
* [X86] Merge the different CMOV instructions for each condition code into ↵Craig Topper2019-04-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an immediate. Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode ↵Craig Topper2018-08-131-39/+12
| | | | | | | | | | | | | | | | selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same. While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day. The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with. While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them. Fixes PR38537. llvm-svn: 339622
* [X86][Disassembler] Fix LOCK prefix disassembler supportMaksim Panchenko2018-07-051-0/+3
| | | | | | | | | | | | | | | | | | | Summary: If LOCK prefix is not the first prefix in an instruction, LLVM disassembler silently drops the prefix. The fix is to select a proper instruction with a builtin LOCK prefix if one exists. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D49001 llvm-svn: 336400
* [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 ↵Craig Topper2018-06-061-1/+1
| | | | | | | | | | are used as the index. These encodings correspond to the cases in the normal encoding scheme where there is no index and our modrm reading code initially decodes it as such. The VSIB handling code tried to compensate for this, but failed to add the base needed to make later code do the right thing. Fixes PR37712. llvm-svn: 334121
* [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg ↵Craig Topper2018-06-011-7/+18
| | | | | | | | encodes a GPR. This is different than the behavior of EVEX.X extending modrm.rm to 5 bits. llvm-svn: 333728
* [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when ↵Craig Topper2018-06-011-0/+1
| | | | | | modrm.rm encodes a k-register. llvm-svn: 333727
* [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.Craig Topper2018-06-011-3/+4
| | | | | | A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. llvm-svn: 333725
* [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of ↵Craig Topper2018-06-011-3/+5
| | | | | | | | | | memory operations. This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3. I think there are still more bugs related to this. llvm-svn: 333722
* [X86][Disassembler] Use a local variable instead of using a field in the ↵Craig Topper2018-06-011-9/+11
| | | | | | instruction object. NFC llvm-svn: 333721
* [X86] Make sure the check for VEX.vvvv being all ones on instructions that ↵Craig Topper2018-06-011-1/+3
| | | | | | don't use it doesn't ignore a bit in 32-bit mode. llvm-svn: 333717
* [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.Craig Topper2018-06-011-2/+2
| | | | llvm-svn: 333714
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-011-2/+4
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-231-4/+2
| | | | llvm-svn: 330640
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-231-2/+4
| | | | | Reviewers: craig.topper llvm-svn: 330638
* [X86] WaitPKG instructionsGabor Buella2018-04-201-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three new instructions: umonitor - Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. umwait - A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. tpause - Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Also modifying the description of the mfence instruction, as the rep prefix (0xF3) was allowed before, which would conflict with umonitor during disassembly. Before: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text mfence After: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text umonitor %rax Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45253 llvm-svn: 330462
* [X86] Disassembler support for having an ADSIZE prefix affect instructions ↵Craig Topper2018-04-051-0/+3
| | | | | | | | with 0xf2 and 0xf3 prefixes. Needed to support umonitor from D45253. llvm-svn: 329327
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-241-41/+17
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-151-2/+43
| | | | | | | | | | | | | | | | | | | Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
* Invalid used of 'w' suffix on push and pop using 64-bit register.Andrew V. Tischenko2017-10-301-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D38626 llvm-svn: 316898
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-231-2/+2
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-231-0/+4
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-22/+37
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-161-139/+126
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* Revert "The current version of LLVM X86 disassembler incorrectly interprets ↵Eric Christopher2017-08-291-68/+17
| | | | | | | | some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed. This reverts commit r311882. llvm-svn: 311987
* The current version of LLVM X86 disassembler incorrectly interprets some ↵Andrew V. Tischenko2017-08-281-17/+68
| | | | | | | | | | | | | | possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs. Differential Revision: https://reviews.llvm.org/D36788 M lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp M lib/Target/X86/Disassembler/X86DisassemblerDecoder.h A test/MC/Disassembler/X86/prefixes-i386.s A test/MC/Disassembler/X86/prefixes-x86_64.s M test/MC/Disassembler/X86/prefixes.txt llvm-svn: 311882
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [X86] Remove unnecessary duplicate code (PR30649). NFCI.Simon Pilgrim2017-03-221-5/+0
| | | | llvm-svn: 298495
* [X86] Reduce the number of operand 'types' the disassembler needs to deal ↵Craig Topper2017-01-161-14/+5
| | | | | | | | | with. NFCI We were frequently checking for a list of types and the different types conveyed no real information. So lump them together explicitly. llvm-svn: 292095
* [AVX-512] Teach the disassembler about all of the EVEX gather and scatter ↵Craig Topper2017-01-161-1/+8
| | | | | | instructions. llvm-svn: 292094
* [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a ↵Craig Topper2017-01-161-0/+6
| | | | | | | | different encoding than regular addressing modes. This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction. llvm-svn: 292093
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-011-6/+6
| | | | llvm-svn: 283018
* [X86] Decode MPX BND registers.Ahmed Bougacha2016-07-141-4/+8
| | | | | | | | | | | | | We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
* [X86] Remove unused encoding types from disassembler. NFCCraig Topper2016-02-211-8/+0
| | | | llvm-svn: 261494
* [X86] Remove unused entries from the disassembler type enum.Craig Topper2016-02-191-1/+0
| | | | llvm-svn: 261311
* Fix Clang-tidy readability-redundant-control-flow warnings; other minor fixes.Eugene Zelenko2016-02-021-3/+0
| | | | | | Differential revision: http://reviews.llvm.org/D16793 llvm-svn: 259539
* [X86] Fix a couple cases were bitwise and logical operations were being ↵Craig Topper2015-12-101-1/+1
| | | | | | mixed. NFC llvm-svn: 255224
* [X86][AVX512CD] add mask broadcast intrinsicsAsaf Badouh2015-11-181-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D14573 llvm-svn: 253450
* [X86] NFC: Clean up and clang-format a few linesVedant Kumar2015-08-281-5/+5
| | | | llvm-svn: 246340
* [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassemblyVedant Kumar2015-08-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for disassembling unusual instruction sequences in 64-bit mode w.r.t the CALL rel16 instruction. It might be desirable to move the check somewhere else, but it essentially mimics the special case handling with JCXZ in 16-bit mode. The current behavior accepts the opcode size prefix and causes the call's immediate to stop disassembling after 2 bytes. When debugging sequences of instructions with this pattern, the disassembler output becomes extremely unreliable and essentially useless (if you jump midway into what lldb thinks is a unified instruction, you'll lose %rip). So we ignore the prefix and consume all 4 bytes when disassembling a 64-bit mode binary. Note: in Vol. 2A 3-99 the Intel spec states that CALL rel16 is N.S. N.S. is defined as: Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. (Vol. 2A 3-7) Since 0x66 is an operand override prefix we should be OK (although we may want to warn about 0x67 prefixes to 0xe8). On the CPUs I tested with, they all ignore the 0x66 prefix in 64-bit mode. Patch by Matthew Barney! Differential Revision: http://reviews.llvm.org/D9573 llvm-svn: 246038
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-9/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* Refactor: Simplify boolean expressions in x86 targetDavid Blaikie2015-03-231-5/+2
| | | | | | | | | | Simplify boolean expressions with `true` and `false` with `clang-tidy` Patch by Richard Thomson. Differential Revision: http://reviews.llvm.org/D8519 llvm-svn: 233002
* [X86] There are only 8 mask registers. Fail disassembly if instruction tries ↵Craig Topper2015-03-021-0/+2
| | | | | | to reference more. llvm-svn: 230931
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-071-2/+0
| | | | llvm-svn: 225343
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