summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-011-6/+6
| | | | llvm-svn: 283018
* [X86] Decode MPX BND registers.Ahmed Bougacha2016-07-141-4/+8
| | | | | | | | | | | | | We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
* [X86] Remove unused encoding types from disassembler. NFCCraig Topper2016-02-211-8/+0
| | | | llvm-svn: 261494
* [X86] Remove unused entries from the disassembler type enum.Craig Topper2016-02-191-1/+0
| | | | llvm-svn: 261311
* Fix Clang-tidy readability-redundant-control-flow warnings; other minor fixes.Eugene Zelenko2016-02-021-3/+0
| | | | | | Differential revision: http://reviews.llvm.org/D16793 llvm-svn: 259539
* [X86] Fix a couple cases were bitwise and logical operations were being ↵Craig Topper2015-12-101-1/+1
| | | | | | mixed. NFC llvm-svn: 255224
* [X86][AVX512CD] add mask broadcast intrinsicsAsaf Badouh2015-11-181-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D14573 llvm-svn: 253450
* [X86] NFC: Clean up and clang-format a few linesVedant Kumar2015-08-281-5/+5
| | | | llvm-svn: 246340
* [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassemblyVedant Kumar2015-08-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for disassembling unusual instruction sequences in 64-bit mode w.r.t the CALL rel16 instruction. It might be desirable to move the check somewhere else, but it essentially mimics the special case handling with JCXZ in 16-bit mode. The current behavior accepts the opcode size prefix and causes the call's immediate to stop disassembling after 2 bytes. When debugging sequences of instructions with this pattern, the disassembler output becomes extremely unreliable and essentially useless (if you jump midway into what lldb thinks is a unified instruction, you'll lose %rip). So we ignore the prefix and consume all 4 bytes when disassembling a 64-bit mode binary. Note: in Vol. 2A 3-99 the Intel spec states that CALL rel16 is N.S. N.S. is defined as: Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. (Vol. 2A 3-7) Since 0x66 is an operand override prefix we should be OK (although we may want to warn about 0x67 prefixes to 0xe8). On the CPUs I tested with, they all ignore the 0x66 prefix in 64-bit mode. Patch by Matthew Barney! Differential Revision: http://reviews.llvm.org/D9573 llvm-svn: 246038
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-9/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* Refactor: Simplify boolean expressions in x86 targetDavid Blaikie2015-03-231-5/+2
| | | | | | | | | | Simplify boolean expressions with `true` and `false` with `clang-tidy` Patch by Richard Thomson. Differential Revision: http://reviews.llvm.org/D8519 llvm-svn: 233002
* [X86] There are only 8 mask registers. Fail disassembly if instruction tries ↵Craig Topper2015-03-021-0/+2
| | | | | | to reference more. llvm-svn: 230931
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-071-2/+0
| | | | llvm-svn: 225343
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-311-0/+26
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* [x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler.Craig Topper2014-12-311-16/+5
| | | | llvm-svn: 225035
* [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble ↵Craig Topper2014-12-261-2/+0
| | | | | | references to them. llvm-svn: 224862
* [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. ↵Craig Topper2014-12-261-5/+1
| | | | | | Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-261-6/+0
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit ↵Craig Topper2014-10-071-0/+47
| | | | | | | | | | mode for certain instructions it shouldn't. Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present. Fixes PR21169. llvm-svn: 219194
* Formatting fixes. Most putting 'else' on the same line as the preceding ↵Craig Topper2014-10-071-38/+19
| | | | | | curly brace. llvm-svn: 219193
* Fix filename in header and use C++ version of the C header files.Craig Topper2014-10-071-5/+5
| | | | llvm-svn: 219192
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-2/+5
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-241-1/+2
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> llvm-svn: 211565
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-281-10/+9
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* [C++] Use 'nullptr'.Craig Topper2014-04-281-2/+2
| | | | llvm-svn: 207394
* C++ has a bool type! (And C's had one too, for 15 years...)Richard Smith2014-04-201-32/+29
| | | | llvm-svn: 206723
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-201-0/+23
| | | | | | and ContextDecision in different source files (depending on #define magic). llvm-svn: 206720
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-201-0/+1819
reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. llvm-svn: 206717
OpenPOWER on IntegriCloud