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rdar://8013734
llvm-svn: 106725
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llvm-svn: 106724
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llvm-svn: 106723
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understand the vcmp instruction
llvm-svn: 106678
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instruction. Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode. Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.
llvm-svn: 105661
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llvm-svn: 105005
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llvm-svn: 105001
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llvm-svn: 104890
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are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
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llvm-svn: 104626
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llvm-svn: 104549
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immediates based on the width of the target instruction. For example:
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
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llvm-svn: 104435
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llvm-svn: 104394
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llvm-svn: 104272
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instructions.
llvm-svn: 104231
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after testing before committing.
llvm-svn: 103681
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llvm-svn: 103677
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lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
llvm-svn: 103668
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llvm-svn: 103535
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instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
llvm-svn: 103015
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- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
llvm-svn: 103012
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in memory operands. rdar://7874844
llvm-svn: 101661
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believe this fixes the last memory leaks under test/MC.
llvm-svn: 99102
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temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
llvm-svn: 98858
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other functionality on 403.gcc compiled at -O0.
llvm-svn: 98405
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llvm-svn: 98394
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llvm-svn: 96055
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x86_32-encoding.s in on expectation of it passing.
llvm-svn: 95806
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llvm-svn: 95634
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llvm-svn: 95627
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for register tokens. Before, if it encountered
'%al,' it would report 'al,' as the token. Now it
correctly reports '%al'.
llvm-svn: 95594
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Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.
llvm-svn: 95252
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some mechanism for specifying alternative syntaxes, but I'm not sure what form
that should take yet.
llvm-svn: 95158
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== 1.
llvm-svn: 95137
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to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
llvm-svn: 94940
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something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
movl $0, %eax
as
movl 0, %eax
Feel free to guess how well that worked.
llvm-svn: 94869
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register, and use to cleanup a FIXME in X86AsmParser.cpp.
llvm-svn: 94859
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llvm-svn: 94502
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TargetAsmLexer.
llvm-svn: 94482
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llvm-svn: 94479
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TargetAsmLexer. Dialect-specific lexing code will
be placed in the functions LexTokenATT() and
LexTokenIntel().
llvm-svn: 94456
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llvm-svn: 94378
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movw $8, (_cost_table_-L97$pb)+66(%eax)
After the parens, we could still have a binop.
llvm-svn: 94345
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llvm-svn: 94278
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target-specific AsmLexer, and added the appropriate
registration calls.
llvm-svn: 94275
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be static. Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.
llvm-svn: 94266
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missing ones are libsupport, libsystem and libvmcore. libvmcore is
currently blocked on bugpoint, which uses EH. Once it stops using
EH, we can switch it off.
This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.
llvm-svn: 94164
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llvm-svn: 94129
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the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
llvm-svn: 93916
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