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* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-5/+6
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* Fix function name per coding standard.Chad Rosier2012-09-051-2/+2
| | | | llvm-svn: 163187
* [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier2012-09-031-2/+3
| | | | | | | the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. llvm-svn: 163124
* [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier2012-09-031-0/+6
| | | | | | MCTargetAsmParser class. llvm-svn: 163122
* Removed unused argument.Chad Rosier2012-09-031-14/+13
| | | | llvm-svn: 163104
* [ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier2012-09-031-9/+18
| | | | | | | | | | MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. llvm-svn: 163101
* The ConvertToMCInst() function can't fail, so remove the now dead ↵Chad Rosier2012-08-311-3/+0
| | | | | | Match_ConversionFail enum. llvm-svn: 163002
* Typo.Chad Rosier2012-08-281-1/+1
| | | | llvm-svn: 162807
* [ms-inline asm] Avoid a false positive assertionChad Rosier2012-08-221-1/+3
| | | | | | | | | | | Assertion failed: (Start.isValid() == End.isValid() && "Start and end should either both be valid or both be invalid!") when parsing inline asm. SMLoc assumes that the first char * in the source is invalid. However, when parsing an inline asm the mnemonic is at this location. I don't want to change SMLoc, so use a trivial workaround. llvm-svn: 162381
* [ms-inline asm] Do not report a Parser error when matching inline assembly.Chad Rosier2012-08-211-14/+25
| | | | llvm-svn: 162306
* [ms-inline asm] Expose the ErrorInfo from the MatchInstructionImpl. In general,Chad Rosier2012-08-211-4/+6
| | | | | | | | | this is the index of the operand that failed to match. Note: This may cause a buildbot failure due to an API mismatch in clang. Should recover with my next commit to clang. llvm-svn: 162295
* [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).Chad Rosier2012-08-091-3/+19
| | | | | | | | | | This new API will be used by clang to parse ms-style inline asms. One goal of this project is to use this style of inline asm for targets other then x86. Therefore, this API needs to be implemented for non-x86 targets at some point in the future. llvm-svn: 161624
* Remove tab characters.Craig Topper2012-07-181-13/+13
| | | | llvm-svn: 160425
* Fix typo in error message and remove some tab characters.Craig Topper2012-07-181-5/+5
| | | | llvm-svn: 160423
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-0/+29
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Whitespace.Chad Rosier2012-06-271-34/+34
| | | | llvm-svn: 159300
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-2/+5
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used ↵Craig Topper2012-03-291-12/+13
| | | | | | with 'v' version of instructions. llvm-svn: 153636
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Change the X86 assembler to not require a segment register on stringKevin Enderby2012-03-131-4/+5
| | | | | | | instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). llvm-svn: 152654
* Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby2012-03-121-0/+19
| | | | | | registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
* Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby2012-03-091-1/+3
| | | | llvm-svn: 152443
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Add assembler dialect attribute in asm parser which lets target specific asm ↵Devang Patel2012-01-311-4/+3
| | | | | | parser change dialect on the fly. llvm-svn: 149396
* Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel2012-01-301-2/+4
| | | | | | code>{ss,sd,ps,pd}, for intel syntax. llvm-svn: 149291
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-10/+24
| | | | llvm-svn: 149270
* Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel2012-01-271-3/+5
| | | | llvm-svn: 149142
* Keep source location information for X86 MCFixup's.Jim Grosbach2012-01-271-0/+3
| | | | llvm-svn: 149106
* Intel Syntax: Extend special hand coded logic, to recognize special ↵Devang Patel2012-01-241-5/+15
| | | | | | instructions, for intel syntax. llvm-svn: 148864
* Fix typo. Devang Patel2012-01-231-1/+1
| | | | llvm-svn: 148751
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+7
| | | | llvm-svn: 148737
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-6/+16
| | | | llvm-svn: 148721
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-4/+16
| | | | llvm-svn: 148712
* Remove unused variables.Benjamin Kramer2012-01-211-2/+0
| | | | llvm-svn: 148635
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-28/+16
| | | | llvm-svn: 148591
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-0/+5
| | | | llvm-svn: 148570
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+78
| | | | llvm-svn: 148489
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-1/+1
| | | | | | displacement. llvm-svn: 148486
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+114
| | | | | | if available. llvm-svn: 148485
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-16/+87
| | | | | | more desirable. llvm-svn: 148431
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+4
| | | | llvm-svn: 148334
* Untabify.Devang Patel2012-01-171-12/+12
| | | | llvm-svn: 148322
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-2/+1
| | | | | | displacement. llvm-svn: 148321
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-51/+113
| | | | llvm-svn: 148312
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