| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 177242
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llvm-svn: 177135
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llvm-svn: 176341
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s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
No functional change intended.
llvm-svn: 175675
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llvm-svn: 175312
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'SIZE' and 'LENGTH' operators.
llvm-svn: 172773
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Part of rdar://12576868
llvm-svn: 172743
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have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141
llvm-svn: 172484
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llvm-svn: 172157
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r172121.
llvm-svn: 172148
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Part of rdar://12991541
llvm-svn: 172121
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address space. Reordered the EmitULEB128IntValue arguments to
make this easier.
llvm-svn: 171949
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This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.
llvm-svn: 171765
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its only user, is gone.
llvm-svn: 170699
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Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
llvm-svn: 169131
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When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
llvm-svn: 167937
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- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
llvm-svn: 167573
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equivalent to [expr1 + expr2]. See test cases for more examples.
rdar://12470392
llvm-svn: 166949
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llvm-svn: 166819
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Part of rdar://12576868
llvm-svn: 166792
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Part of rdar://12576868
llvm-svn: 166790
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operator.
llvm-svn: 166779
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llvm-svn: 166724
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AsmParser logic. To be used/tested in a subsequent commit.
llvm-svn: 166714
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llvm-svn: 166698
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[register].field
The operator returns the value at the location pointed to by register plus the
offset of field within its structure or union. This patch only handles
immediate fields (i.e., [eax].4). The original displacement has to be a
MCConstantExpr as well.
Part of rdar://12470415 and rdar://12470514
llvm-svn: 166632
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llvm-svn: 166630
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see the offsetof operator. Previously, we were matching something like MOVrm
in the front-end and later matching MOVrr in the back-end. This change makes
things more consistent. It also fixes cases where we can't match against a
memory operand as the source (test cases coming).
Part of rdar://12470317
llvm-svn: 166592
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pointer, not the size of the variable.
Part of rdar://12470317
llvm-svn: 166526
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llvm-svn: 166525
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non-zero value as we don't know the actual value at this point. This is
necessary to get the matching correct in some cases. However, the actual value
set as the base register doesn't matter, since we're just matching not emitting.
llvm-svn: 166523
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on patch to r166433.
rdar://12470317
llvm-svn: 166488
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Part of rdar://12470317
llvm-svn: 166436
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CodeGen in the front-end not implemented yet.
rdar://12470317
llvm-svn: 166433
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llvm-svn: 166349
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a memory operand. Retain this information and then add the sizing directives
to the IR. This allows the backend to do proper instruction selection.
llvm-svn: 166316
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an instruction.
llvm-svn: 165955
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llvm-svn: 165947
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the interface between the front-end and the MC layer when parsing inline
assembly. Unfortunately, this is too deep into the parsing stack. Specifically,
we're unable to handle target-independent assembly (i.e., assembly directives,
labels, etc.). Note the MatchAndEmitInstruction() isn't the correct
abstraction either. I'll be exposing target-independent hooks shortly, so this
is really just a cleanup.
llvm-svn: 165858
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llvm-svn: 165847
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MapAndConstraints vector. Also remove the unused Kind argument.
llvm-svn: 165833
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llvm-svn: 165324
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segmented registers. Test case to come.
llvm-svn: 165275
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llvm-svn: 165069
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of operand is specific to MS-style inline assembly and should not be generated
when parsing normal assembly.
The purpose of the wildcard operands are to allow the AsmParser to match
multiple instructions (i.e., MCInsts) to a given ms-style asm statement. For
the time being the matcher just returns the first match. This patch only
implements wildcard matches for memory operands. Support for register
wildcards will be added in the near future.
llvm-svn: 165057
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map constraints and MCInst operands to inline asm operands. This replaces the
getMCInstOperandNum() function.
The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.
llvm-svn: 164979
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llvm-svn: 164611
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Also remove an unused argument.
llvm-svn: 164567
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llvm-svn: 164548
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llvm-svn: 164420
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