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* X86AsmParser.cpp: Fix memory leak at replacing movsd to movsl.NAKAMURA Takumi2014-04-231-1/+3
| | | | llvm-svn: 206991
* Create MCTargetOptions.Evgeniy Stepanov2014-04-233-19/+26
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* AddressSanitizer instrumentation for MOV and MOVAPS.Evgeniy Stepanov2014-03-144-3/+304
| | | | | | | | This is an initial version of *Sanitizer instrumentation of assembly code. Patch by Yuri Gorshenin. llvm-svn: 203908
* Use printable names to implement directional labels.Rafael Espindola2014-03-131-2/+1
| | | | | | | | | | | | | | This changes the implementation of local directional labels to use a dedicated map. With that it can then just use CreateTempSymbol, which is what the rest of MC uses. CreateTempSymbol doesn't do a great job at making sure the names are unique (or being efficient when the names are not needed), but that should probably be fixed in a followup patch. This fixes pr18928. llvm-svn: 203826
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-092-19/+19
| | | | | | class. llvm-svn: 203418
* MS asm: The initial dot in struct access is optionalReid Kleckner2014-03-061-8/+17
| | | | | | | | Fixes PR18994. Tests, once again, in that other repository. =P llvm-svn: 203146
* MS asm: Attempt to parse variables followed by a bracketed displacementReid Kleckner2014-03-041-2/+34
| | | | | | | | | | This is required to include MSVC's <atomic> header, which we do now in LLVM. Tests forthcoming in Clang, since that's where we test semantic inline asm changes. llvm-svn: 202865
* MC: Fix Intel assembly parser for [global + offset]Reid Kleckner2014-03-041-15/+27
| | | | | | | | | We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. llvm-svn: 202774
* X86Operand is extracted into individual header.Evgeniy Stepanov2014-02-283-497/+533
| | | | | | | | | | X86Operand is extracted into individual header, because it allows to create an arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline assembly instrumentation. Patch by Yuri Gorshenin. llvm-svn: 202496
* AVX-512: Fixed compilation issueElena Demikhovsky2014-02-201-4/+7
| | | | llvm-svn: 201761
* AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by ↵Elena Demikhovsky2014-02-201-63/+99
| | | | | | | | Nis Zinovy (zinovy.y.nis@intel.com) Fixed truncate i32 to i1; a test will be provided in the next commit. llvm-svn: 201757
* Update the X86 assembler for .intel_syntax to acceptKevin Enderby2014-02-061-6/+64
| | | | | | | | the << and >> bitwise operators. rdar://15975725 llvm-svn: 200896
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-3/+3
| | | | llvm-svn: 200345
* Update the X86 assembler for .intel_syntax to produce an error for invalid baseKevin Enderby2014-01-231-32/+48
| | | | | | | | | registers in memory addresses that do not match the index register. As it does for .att_syntax. rdar://15887380 llvm-svn: 199948
* Update the X86 assembler for .intel_syntax to produce an error for invalidKevin Enderby2014-01-231-3/+11
| | | | | | | | | | | scale factors in memory addresses. As it does for .att_syntax. It was producing: Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133. rdar://14967214 llvm-svn: 199942
* [x86] Remove now-unused isSrcOp() and isDstOp() from X86AsmParserDavid Woodhouse2014-01-221-30/+0
| | | | llvm-svn: 199810
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-221-10/+11
| | | | llvm-svn: 199809
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-221-10/+10
| | | | llvm-svn: 199808
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-221-13/+26
| | | | llvm-svn: 199807
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+47
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)David Woodhouse2014-01-221-0/+8
| | | | llvm-svn: 199805
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-29/+39
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-29/+41
| | | | llvm-svn: 199803
* Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.Craig Topper2014-01-171-0/+1
| | | | llvm-svn: 199477
* Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.Craig Topper2014-01-171-0/+1
| | | | llvm-svn: 199476
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-5/+6
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Update the X86 assembler for .intel_syntax to acceptKevin Enderby2014-01-151-7/+63
| | | | | | | | the | and & bitwise operators. rdar://15570412 llvm-svn: 199323
* correct target directive handling error handlingSaleem Abdulrasool2014-01-131-9/+10
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. llvm-svn: 199068
* [x86] Make AsmParser validate registers for memory operands a bit betterDavid Woodhouse2014-01-081-3/+38
| | | | | | | | | | | | We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
* [x86] Add basic support for .code16Craig Topper2014-01-061-11/+33
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-0/+1
| | | | llvm-svn: 198013
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-1/+1
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-191-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197744
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-191-34/+2
| | | | | | directional labels. Because it doesn't work for windows :) llvm-svn: 197731
* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-191-2/+34
| | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197728
* Introduce poor man's consumeToken() in X86AsmParserAlp Toker2013-12-021-18/+13
| | | | | | | | This makes the code a little more idiomatic. No change in behaviour. llvm-svn: 196113
* Revamp error checking in the ms inline asm parser.Benjamin Kramer2013-12-011-46/+47
| | | | | | | | | - Actually abort when an error occurred. - Check that the frontend lookup worked when parsing length/size/type operators. Tested by a clang test. PR18096. llvm-svn: 196044
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi2013-11-281-2/+0
| | | | | | I forgot to commit them. They were staging in my local repo. llvm-svn: 195924
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+37
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-071-0/+49
| | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. llvm-svn: 192088
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-121-0/+41
| | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. llvm-svn: 190595
* [ms-inline asm] Support offsets after segment registersDavid Majnemer2013-08-271-40/+70
| | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 llvm-svn: 189407
* Remove some unnecessary PredicateMethod overrides. Add RenderMethod ↵Craig Topper2013-08-261-56/+0
| | | | | | overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
* Put some of the AVX-512 parsing stuff in a more consistent place with the ↵Craig Topper2013-08-251-11/+9
| | | | | | existing functions. llvm-svn: 189204
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-0/+39
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Use pop_back() instead of pop_back_val() when the returned value is not used.Jakub Staszak2013-08-081-4/+4
| | | | llvm-svn: 187986
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+22
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-241-0/+1
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
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