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path: root/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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* simplify the hacks around jrcxz.Chris Lattner2010-09-061-4/+1
| | | | llvm-svn: 113167
* have tblgen detect when an instruction would have matched, butChris Lattner2010-09-061-34/+44
| | | | | | | | | | | | | failed because a subtarget feature was not enabled. Use this to remove a bunch of hacks from the X86AsmParser for rejecting things like popfl in 64-bit mode. Previously these hacks weren't needed, but were important to get a message better than "invalid instruction" when used in the wrong mode. This also fixes bugs where pushal would not be rejected correctly in 32-bit mode (just pusha). llvm-svn: 113166
* change MatchInstructionImpl to return an enum instead of bool.Chris Lattner2010-09-061-5/+5
| | | | llvm-svn: 113165
* have AsmMatcherEmitter.cpp produce the hunk of code that gets includedChris Lattner2010-09-061-9/+9
| | | | | | | into the middle of the class, and rework how the different sections of the generated file are conditionally included for simplicity. llvm-svn: 113163
* random cleanupsChris Lattner2010-09-061-9/+12
| | | | llvm-svn: 113157
* MC/X86: Tweak imul recognition, previous hack only applies for the imul formDaniel Dunbar2010-08-241-1/+3
| | | | | | taking immediates. llvm-svn: 111950
* MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.Daniel Dunbar2010-08-241-0/+8
| | | | llvm-svn: 111947
* MC/X86: Warn on scale factors > 1 without index register, instead of erroring,Daniel Dunbar2010-08-241-3/+4
| | | | | | for 'as' compatibility. llvm-svn: 111945
* remove some code that is dead now that lea's are modeled with segment registers.Chris Lattner2010-08-181-14/+0
| | | | llvm-svn: 111343
* MC/X86/AsmParser: Give an explicit error message when we reject an instructionDaniel Dunbar2010-08-121-2/+31
| | | | | | because it could have an ambiguous suffix. llvm-svn: 110890
* MC/AsmParser: Push the burdon of emitting diagnostics about unmatchedDaniel Dunbar2010-08-121-12/+19
| | | | | | instructions onto the target specific parser, which can do a better job. llvm-svn: 110889
* MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar2010-08-111-0/+2
| | | | llvm-svn: 110790
* Support x86 "eiz" and "riz" pseudo index registers in the assembler.Bruno Cardoso Lopes2010-07-241-1/+15
| | | | llvm-svn: 109295
* Remove trailing whitespaceBruno Cardoso Lopes2010-07-231-30/+30
| | | | llvm-svn: 109276
* Add AVX version of CLMUL instructionsBruno Cardoso Lopes2010-07-231-0/+17
| | | | llvm-svn: 109248
* MC/X86: We now match instructions like "incl %eax" correctly for the arch we areDaniel Dunbar2010-07-191-53/+0
| | | | | | assembling; remove crufty custom cleanup code. llvm-svn: 108681
* TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> ↵Daniel Dunbar2010-07-191-4/+12
| | | | | | | | attributes as part of the matcher. - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86. llvm-svn: 108677
* Target: Give the TargetAsmParser access to the TargetMachine.Daniel Dunbar2010-07-191-6/+7
| | | | | | - Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this. llvm-svn: 108664
* Don't pass StringRef by reference.Benjamin Kramer2010-07-141-2/+2
| | | | llvm-svn: 108366
* Added a check that pusha cannot be encoded in 64-bit mode.Kevin Enderby2010-07-131-0/+2
| | | | llvm-svn: 108265
* Add more assembly opcodes for SSE compare instructionsBruno Cardoso Lopes2010-07-071-8/+32
| | | | llvm-svn: 107823
* Teach the x86 mc assembler that %dr6 = %db6, this implementsChris Lattner2010-06-241-0/+22
| | | | | | rdar://8013734 llvm-svn: 106725
* Add tests for different AVX cmp opcodes, also teach the x86 asm parser to ↵Bruno Cardoso Lopes2010-06-231-6/+8
| | | | | | understand the vcmp instruction llvm-svn: 106678
* Incremental improvement to the handling of the x86 "Jump if rCX Zero"Kevin Enderby2010-06-081-0/+14
| | | | | | | | | | | | instruction. Added the 64-bit version "jrcxz" so it is recognized and also added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in 32-bit mode. Still to do is to correctly handle the encoding of the instruction adding the Address-size override prefix byte, 0x67, when the width of the count register is not the same as the mode the machine is running in. Which for example means the encoding of "jecxz" depends if you are assembling as a 32-bit target or a 64-bit target. llvm-svn: 105661
* MC/X86: Add alias for movzx.Kevin Enderby2010-05-281-0/+1
| | | | llvm-svn: 105005
* MC/X86: Add alias for fwait.Kevin Enderby2010-05-281-0/+1
| | | | llvm-svn: 105001
* MC/X86: Add aliases for Jcc variants.Kevin Enderby2010-05-271-0/+13
| | | | llvm-svn: 104890
* Changed the encoding of X86 floating point stack operations where both operandsKevin Enderby2010-05-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. llvm-svn: 104634
* MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.Daniel Dunbar2010-05-251-1/+36
| | | | llvm-svn: 104626
* MC/X86: Add aliases for CMOVcc variants.Kevin Enderby2010-05-241-0/+14
| | | | llvm-svn: 104549
* MC/X86: Subdivide immediates a bit more, so that we properly recognize ↵Daniel Dunbar2010-05-221-29/+56
| | | | | | | | | | | immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
* MC/X86: Add alias for setz, setnz, jz, jnz.Daniel Dunbar2010-05-221-0/+4
| | | | llvm-svn: 104435
* Added retl for 32-bit x86 and added retq for 64-bit x86.Kevin Enderby2010-05-211-0/+2
| | | | llvm-svn: 104394
* X86: Model i64i32imm properly, as a subclass of all immediates.Daniel Dunbar2010-05-201-0/+20
| | | | llvm-svn: 104272
* Fix assembly parsing and encoding of the pushf and popf family ofDan Gohman2010-05-201-0/+17
| | | | | | instructions. llvm-svn: 104231
* reapply r103668 with a fix. Never make "minor syntax changes"Chris Lattner2010-05-131-0/+33
| | | | | | after testing before committing. llvm-svn: 103681
* revert r103668 for now, it is apparently breaking things.Chris Lattner2010-05-121-33/+0
| | | | llvm-svn: 103677
* moffset forms of moves are x86-32 only, make the parserChris Lattner2010-05-121-0/+33
| | | | | | | | lower them to the correct x86-64 instructions since we don't have a clean way to handle this in td files yet. rdar://7947184 llvm-svn: 103668
* MC/X86: Extend suffix matching hack to match 'q' suffix.Daniel Dunbar2010-05-121-1/+3
| | | | llvm-svn: 103535
* MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form ofDaniel Dunbar2010-05-041-5/+0
| | | | | | | | | | | | | | | instructions which have no direct register usage. Darwin 'as' accepts: add $0, (%rax) but rejects mov $0, (%rax) for example. Given that, only accept suffix matches which match exactly one form. We still need to emit nice diagnostics for failures... llvm-svn: 103015
* MC/X86: Add "support" for matching ATT style mnemonic prefixes.Daniel Dunbar2010-05-041-2/+63
| | | | | | | | | | | | | | | | | - The idea is that when a match fails, we just try to match each of +'b', +'w', +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept it. If all match, we assume it is width generic, and take the 'l' form. - This would be a horrible hack, if it weren't so simple. Therefore it is an elegant solution! Chris gets the credit for this particular elegant solution. :) - Next step to making this more robust is to have the X86 matcher generate the mnemonic prefix information. Ideally we would also compute up-front exactly which mnemonic to attempt to match, but this may require more custom code in the matcher than is really worth it. llvm-svn: 103012
* teach the x86 asm parser how to handle segment prefixesChris Lattner2010-04-171-12/+17
| | | | | | in memory operands. rdar://7874844 llvm-svn: 101661
* MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I ↵Daniel Dunbar2010-03-201-1/+3
| | | | | | believe this fixes the last memory leaks under test/MC. llvm-svn: 99102
* MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement aDaniel Dunbar2010-03-181-3/+42
| | | | | | | | temporary workaround for matching inc/dec on x86_64 to the correct instruction. - This hack will eventually be replaced with a robust mechanism for handling matching instructions based on the available target features. llvm-svn: 98858
* MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testingDaniel Dunbar2010-03-131-0/+9
| | | | | | other functionality on 403.gcc compiled at -O0. llvm-svn: 98405
* MC/X86: Push immediate operands as immediates not expressions when possible.Daniel Dunbar2010-02-131-4/+12
| | | | llvm-svn: 96055
* MC/X86 AsmMatcher: Fix a use after free spotted by d0k, and de-XFAILDaniel Dunbar2010-02-101-18/+15
| | | | | | x86_32-encoding.s in on expectation of it passing. llvm-svn: 95806
* Implement x86 asm parsing support for %st and %st(4)Chris Lattner2010-02-091-0/+35
| | | | llvm-svn: 95634
* pass stringref by value instead of by const&Chris Lattner2010-02-091-1/+2
| | | | llvm-svn: 95627
* Added support for X86 instruction prefixes so llvm-mc can assemble them. TheKevin Enderby2010-02-031-2/+12
| | | | | | | | | | Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
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