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* [WebAssembly] CodeGen support for __builtin_wasm_page_size()Dan Gohman2015-08-242-1/+8
| | | | llvm-svn: 245872
* [WebAssembly] Skeleton FastISel supportDan Gohman2015-08-245-0/+97
| | | | llvm-svn: 245860
* [WebAssembly] Implement floating point rounding operators.Dan Gohman2015-08-242-12/+16
| | | | llvm-svn: 245859
* [WebAssembly] Tell TargetTransformInfo about popcnt and sqrt.Dan Gohman2015-08-242-4/+10
| | | | llvm-svn: 245853
* [WebAssembly] Use the checked form of MachineFunction::getSubtarget. NFC.Dan Gohman2015-08-242-4/+3
| | | | llvm-svn: 245852
* [WebAssembly] Implement the is_zero_undef forms of cttz and ctlzDan Gohman2015-08-241-0/+6
| | | | llvm-svn: 245851
* [WebAssembly] Mark more operators as Expand.Dan Gohman2015-08-201-0/+26
| | | | llvm-svn: 245636
* [WebAssembly] Use the default alignment for SIMD types.Dan Gohman2015-08-191-2/+2
| | | | | | | | | Previously WebAssembly's datalayout string had -v128:8:128. This had been an attempt to declare a certain level of support for unaligned SIMD accesses. However, clang makes its own determinations for SIMD alignment that are independent of the datalayout string, so this wasn't actually meaningful. llvm-svn: 245494
* [WebAssembly] Add RelooperJF Bastien2015-08-153-0/+1121
| | | | | | | | | | | | | | | | This is just an initial checkin of an implementation of the Relooper algorithm, in preparation for WebAssembly codegen to utilize. It doesn't do anything yet by itself. The Relooper algorithm takes an arbitrary control flow graph and generates structured control flow from that, utilizing a helper variable when necessary to handle irreducibility. The WebAssembly backend will be able to use this in order to generate an AST for its binary format. Author: azakai Reviewers: jfb, sunfish Subscribers: jevinskie, arsenm, jroelofs, llvm-commits Differential revision: http://reviews.llvm.org/D11691 llvm-svn: 245142
* WebAssembly: floating-point comparisonsJF Bastien2015-08-122-0/+16
| | | | | | | | | | | | | | | | | | Summary: D11924 implemented part of the floating-point comparisons, this patch implements the rest: * Tell ISelLowering that all booleans are either 0 or 1. * Expand the eq/ne/lt/le/gt/ge floating-point comparisons to the canonical ones (similar to what Mips32r6InstrInfo.td does). * Add tests for ord/uno. * Add tests for ueq/one/ult/ule/ugt/uge. * Fix existing comparison tests to remove the (res & 1) code, which setBooleanContents stops from generating. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11970 llvm-svn: 244779
* WebAssembly: implement comparison.JF Bastien2015-08-114-25/+36
| | | | | | | | | | | | Some of the FP comparisons (ueq, one, ult, ule, ugt, uge) are currently broken, I'll fix them in a follow-up. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11924 llvm-svn: 244665
* WebAssembly: implement WebAssemblyTargetLowering::getTargetNodeNameJF Bastien2015-08-112-1/+13
| | | | | | | | | | Summary: Implementation is the same as in AArch64. Subscribers: aemerson, jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11956 llvm-svn: 244655
* Use llvm::make_unique to fix the MSVC build.Rafael Espindola2015-08-111-1/+1
| | | | llvm-svn: 244641
* WebAssembly: NFC fix release build break, unused variable.JF Bastien2015-08-111-0/+1
| | | | | | | | | | Summary: Caused by D11914, pointed out by blaikie. Subscribers: llvm-commits, jfb, dblaikie Differential Revision: http://reviews.llvm.org/D11929 llvm-svn: 244570
* WebAssembly: add basic floating-point testsJF Bastien2015-08-111-4/+8
| | | | | | | | | | Summary: I somehow forgot to add these when I added the basic floating-point opcodes. Also remove ceil/floor/trunc/nearestint for now, and add them only when properly tested. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11927 llvm-svn: 244562
* WebAssembly: simply assert on SNaN and NaNs with payloadsJF Bastien2015-08-111-4/+5
| | | | | | | | | | Summary: convertToHexString doesn't represent them correctly at this point in time. This is a follow-up to sunfish's suggestion in D11914. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11925 llvm-svn: 244551
* WebAssembly: print immediatesJF Bastien2015-08-103-20/+42
| | | | | | | | | | | | | | | Summary: For now output using C99's hexadecimal floating-point representation. This patch also cleans up how machine operands are printed: instead of special-casing per type of machine instruction, the code now handles operands generically. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11914 llvm-svn: 244520
* WebAssembly: textual emission uses expected opcode namesJF Bastien2015-08-071-12/+13
| | | | | | | | | | | | Summary: WebAssembly's tablegen instructions have the names WebAssembly expects, but by LLVM convention they're uppercase and suffixed with their type after an underscore. Leave the C++ code that way, but print outt he names WebAssembly expects (lowercase, no type). We could teach tablegen to do this later, maybe by using `!cast<string>(node)` in the .td files. Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11776 llvm-svn: 244305
* WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, ↵JF Bastien2015-08-032-0/+7
| | | | | | | | | | | | with type Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!). Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11715 llvm-svn: 243860
* WebAssembly: handle more than int32 argument/returnJF Bastien2015-08-014-8/+30
| | | | | | | | | | | | Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11699 llvm-svn: 243822
* WebAssembly: handle `ret void`.JF Bastien2015-07-313-3/+3
| | | | | | | | | | | | | | | Summary: Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret! The next step will be to handle other local types (not just int32). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11692 llvm-svn: 243783
* WebAssembly: handle unused function arguments.JF Bastien2015-07-311-4/+6
| | | | | | | | Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11684 llvm-svn: 243770
* WebAssembly: print basic integer assembly.JF Bastien2015-07-316-10/+134
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all ↵Nick Lewycky2015-07-291-1/+1
| | | | | | | | the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.) Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h. llvm-svn: 243585
* WebAssembly: MCAsmInfo only has one syntax variant for now.JF Bastien2015-07-281-5/+3
| | | | | | | | | | Summary: MCAsmInfo is set up with the default AssemblerDialect, which is zero. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11567 llvm-svn: 243452
* WebAssembly: add a generic CPUJF Bastien2015-07-271-0/+3
| | | | | | | | | | Summary: WebAssemblySubtarget.cpp expects a default 'generic' CPU to exist, and this seems to be prevalent with other targets. It makes sense to have something between MVP and bleeding-edge, even though for now it's the same as MVP. This removes a warning that's currently generated. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11546 llvm-svn: 243345
* WebAssembly: more MCAsmInfo nits.JF Bastien2015-07-271-5/+1
| | | | | | | | | | Summary: As suggested by sunfish. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11544 llvm-svn: 243339
* WebAssembly: minor MCAsmInfo fixesJF Bastien2015-07-271-1/+8
| | | | | | | | | | | | Summary: Fix pointer / callee-save stack sto size. Update comment character to be LISP-ish. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11537 llvm-svn: 243326
* WebAssembly: basic bitcode → assembly CodeGen testJF Bastien2015-07-2215-18/+310
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
* Targets: commonize some stack realignment codeJF Bastien2015-07-202-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* Remove DataLayout from TargetLoweringObjectFile, redirect to ModuleMehdi Amini2015-07-161-1/+1
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11079 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242385
* WebAssembly: fix build breakage.JF Bastien2015-07-142-5/+6
| | | | | | | | | | | | | | | Summary: processFunctionBeforeCalleeSavedScan was renamed to determineCalleeSaves and now takes a BitVector parameter as of rL242165, reviewed in http://reviews.llvm.org/D10909 WebAssembly is still marked as experimental and therefore doesn't build by default. It does, however, grep by default! I notice that processFunctionBeforeCalleeSavedScan is still mentioned in a few comments and error messages, which I also fixed. Reviewers: qcolombet, sunfish Subscribers: jfb, dsanders, hfinkel, MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D11199 llvm-svn: 242242
* WebAssembly: add basic int/fp instruction codegen.JF Bastien2015-07-143-28/+63
| | | | | | | | | | | | Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11193 llvm-svn: 242201
* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-1016-19/+331
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* Unbreak WebAssembly buildJF Bastien2015-07-094-26/+6
| | | | | | | | | | | | Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed. Reviewers: sunfish, joker.eph, echristo Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11084 llvm-svn: 241859
* [WebAssembly] Set the scheduling preference.Dan Gohman2015-07-071-0/+2
| | | | llvm-svn: 241637
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* [WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.Dan Gohman2015-07-021-1/+5
| | | | llvm-svn: 241302
* WebAssembly: start instructionsJF Bastien2015-07-018-13/+31
| | | | | | | | | | | | | | | | | | | | Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
* [WebAssembly] Define separate Target instances for 32-bit and 64-bit.Dan Gohman2015-07-014-6/+9
| | | | llvm-svn: 241193
* [WebAssembly] Initial WebAssembly backendDan Gohman2015-06-2947-0/+1839
This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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