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* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-1016-19/+331
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* Unbreak WebAssembly buildJF Bastien2015-07-094-26/+6
| | | | | | | | | | | | Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed. Reviewers: sunfish, joker.eph, echristo Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11084 llvm-svn: 241859
* [WebAssembly] Set the scheduling preference.Dan Gohman2015-07-071-0/+2
| | | | llvm-svn: 241637
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* [WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.Dan Gohman2015-07-021-1/+5
| | | | llvm-svn: 241302
* WebAssembly: start instructionsJF Bastien2015-07-018-13/+31
| | | | | | | | | | | | | | | | | | | | Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
* [WebAssembly] Define separate Target instances for 32-bit and 64-bit.Dan Gohman2015-07-014-6/+9
| | | | llvm-svn: 241193
* [WebAssembly] Initial WebAssembly backendDan Gohman2015-06-2947-0/+1839
This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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