| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | WebAssembly: start instructions | JF Bastien | 2015-07-01 | 1 | -3/+9 |
| | | | | | | | | | | | | | | | | | | | | | Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211 | ||||
| * | [WebAssembly] Define separate Target instances for 32-bit and 64-bit. | Dan Gohman | 2015-07-01 | 1 | -1/+2 |
| | | | | | llvm-svn: 241193 | ||||
| * | [WebAssembly] Initial WebAssembly backend | Dan Gohman | 2015-06-29 | 1 | -0/+166 |
| This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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