|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.
Patch produced by
  for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done
Differential Revision: https://reviews.llvm.org/D46290
llvm-svn: 331272 | 
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| | Summary:
Add a llc command line option and WebAssembly architecture feature for
exception handling.
Reviewers: dschuff
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D43683
llvm-svn: 326004 | 
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| | Sign-extension opcodes have been split into a separate proposal from
the main threads proposal, so switch them to their own target
feature. See:
https://github.com/WebAssembly/sign-extension-ops
llvm-svn: 322966 | 
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| | This adds code to protect WebAssembly's `trunc_s` family of opcodes
from values outside their domain. Even though such conversions have
full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do
not, and only return undef.
This also implements the proposed non-trapping float-to-int conversion
feature and uses that instead when available.
llvm-svn: 319128 | 
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| | Summary:
This tracks the WebAssembly threads feature proposal at
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md
Differential Revision: https://reviews.llvm.org/D37300
llvm-svn: 312145 | 
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| | llvm-svn: 269976 | 
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| | llvm-svn: 258692 | 
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| | experiment with.
llvm-svn: 254856 | 
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| | Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.
Reviewers: sunfish, joker.eph, echristo
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11084
llvm-svn: 241859 | 
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| | Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.
Test Plan: ninja check
Reviewers: sunfish
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10880
llvm-svn: 241211 | 
|  | This WebAssembly backend is just a skeleton at this time and is not yet
functional.
llvm-svn: 241022 |