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* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-101-3/+4
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* WebAssembly: start instructionsJF Bastien2015-07-011-0/+2
| | | | | | | | | | | | | | | | | | | | Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
* [WebAssembly] Initial WebAssembly backendDan Gohman2015-06-291-0/+44
This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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