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* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* Rename AttributeSet to AttributeListReid Kleckner2017-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This class is a list of AttributeSetNodes corresponding the function prototype of a call or function declaration. This class used to be called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is typically accessed by parameter and return value index, so "AttributeList" seems like a more intuitive name. Rename AttributeSetImpl to AttributeListImpl to follow suit. It's useful to rename this class so that we can rename AttributeSetNode to AttributeSet later. AttributeSet is the set of attributes that apply to a single function, argument, or return value. Reviewers: sanjoy, javed.absar, chandlerc, pete Reviewed By: pete Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits Differential Revision: https://reviews.llvm.org/D31102 llvm-svn: 298393
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-2/+2
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [WebAssembly] Don't expand divisions by constants.Dan Gohman2016-05-181-0/+1
| | | | | | | Don't expand divisions by constants if it would require multiple instructions. The current assumption is that engines will perform the desired optimizations. llvm-svn: 269930
* [WebAssembly] Implement __builtin_frame_address.Dan Gohman2016-02-161-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D17307 llvm-svn: 261032
* [WebAssembly] Insert COPY_LOCAL between CopyToReg and FrameIndex DAG nodesDerek Schuff2016-02-161-0/+1
| | | | | | | | | | | | | | CopyToReg nodes don't support FrameIndex operands. Other targets select the FI to some LEA-like instruction, but since we don't have that, we need to insert some kind of instruction that can take an FI operand and produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy copy_local between Op and its FI operand. This results in a redundant copy which we should optimize away later (maybe in the post-FI-lowering peephole pass). Differential Revision: http://reviews.llvm.org/D17213 llvm-svn: 260987
* [WebAssembly] Reformat WebAssemblyFrameLowering and WebAssemblyISelLoweringDerek Schuff2016-02-111-8/+8
| | | | | | | | | | Reviewers: sunfish, jfb Subscribers: jfb, dschuff Differential Revision: http://reviews.llvm.org/D17156 llvm-svn: 260585
* [WebAssembly] Implement unaligned loads and stores.Dan Gohman2016-01-261-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
* [WebAssembly] Implement instruction selection for constant offsets in addresses.Dan Gohman2015-12-151-0/+2
| | | | | | | | | | | | | | | | | | | | Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
* [WebAssembly] Implement prolog/epilog insertion and FrameIndex eliminationDerek Schuff2015-12-111-0/+1
| | | | | | | | | | | | | | | | | | Summary: Use the SP32 physical register as the base for FrameIndex lowering. Update it and the __stack_pointer global var in the prolog and epilog. Extend the mapping of virtual registers to wasm locals to include the physical registers. Rather than modify the target-independent PrologEpilogInserter (which asserts that there are no virtual registers left) include a slightly-modified copy for Wasm that does not have this assertion and only clears the virtual registers if scavenging was needed (which of course it isn't for wasm). Differential Revision: http://reviews.llvm.org/D15344 llvm-svn: 255392
* [WebAssembly] Initial varargs support.Dan Gohman2015-12-041-0/+1
| | | | | | | | | Full varargs support will depend on prologue/epilogue support, but this patch gets us started with most of the basic infrastructure. Differential Revision: http://reviews.llvm.org/D15231 llvm-svn: 254799
* [WebAssembly] Support for register stackifying with load and store instructions.Dan Gohman2015-11-251-0/+1
| | | | llvm-svn: 254076
* [WebAssembly] Implement isCheapToSpeculateCtlz and isCheapToSpeculateCttz.Dan Gohman2015-11-191-0/+2
| | | | | | | This unbreaks test/CodeGen/WebAssembly/i32.ll and test/CodeGen/WebAssembly/i64.ll after r224899. llvm-svn: 253617
* [WebAssembly] Inline asm support.Dan Gohman2015-11-131-0/+3
| | | | llvm-svn: 252997
* [WebAssembly] Check in an initial CFG Stackifier passDan Gohman2015-09-161-0/+2
| | | | | | | | | | | | This pass implements a simple algorithm for conversion from CFG to wasm's structured control flow. It doesn't yet handle multiple-entry loops; that will be added in a future patch. It also adds initial support for switch statements. Differential Revision: http://reviews.llvm.org/D12735 llvm-svn: 247818
* WebAssembly: Implement callJF Bastien2015-08-241-8/+10
| | | | | | | | | | | | Summary: Support function calls. Reviewers: sunfish, sunfishcode Subscribers: sunfishcode, jfb, llvm-commits Differential revision: http://reviews.llvm.org/D12219 llvm-svn: 245887
* Revert two bad commits.JF Bastien2015-08-241-6/+3
| | | | | | | | | | Summary: I forgot to squash git commits before doing an svn dcommit of D12219. Reverting, and re-submitting. Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D12298 llvm-svn: 245886
* callJF Bastien2015-08-241-3/+6
| | | | llvm-svn: 245882
* [WebAssembly] Skeleton FastISel supportDan Gohman2015-08-241-0/+8
| | | | llvm-svn: 245860
* WebAssembly: implement WebAssemblyTargetLowering::getTargetNodeNameJF Bastien2015-08-111-1/+3
| | | | | | | | | | Summary: Implementation is the same as in AArch64. Subscribers: aemerson, jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11956 llvm-svn: 244655
* WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, ↵JF Bastien2015-08-031-0/+2
| | | | | | | | | | | | with type Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!). Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11715 llvm-svn: 243860
* WebAssembly: print basic integer assembly.JF Bastien2015-07-311-0/+2
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* WebAssembly: basic bitcode → assembly CodeGen testJF Bastien2015-07-221-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
* [WebAssembly] Initial WebAssembly backendDan Gohman2015-06-291-0/+49
This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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