summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/TargetRegisterInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-281-248/+0
| | | | | | | | | | | | | | | | The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+4
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Add a PrintRegUnit helper similar to PrintReg.Jakob Stoklund Olesen2012-05-311-0/+21
| | | | | | | | | | | Reg-units are named after their root registers, and most units have a single root, so they simply print as 'AL', 'XMM0', etc. The rare dual root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ... The printing piggybacks on the existing register name tables, so no extra const data space is required. llvm-svn: 157754
* Remove unused variable to silence compiler warning.Richard Trieu2012-05-091-1/+0
| | | | llvm-svn: 156456
* Use a shared function for a common operation.Jakob Stoklund Olesen2012-05-081-26/+5
| | | | llvm-svn: 156441
* Fix bug in TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+1
| | | | | | Test cases for this code are coming. It is not used for anything yet. llvm-svn: 156327
* Add TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This function is a generalization of getMatchingSuperRegClass() to the symmetric case where both sides are using a sub-register index. It will find a super-register class and sub-register indexes that make this diagram commute: PreA SuperRC ----------> RCA | | | | PreB | | SubA | | | | V V RCB ----------> SubRC SubB This can be used to coalesce copies like: %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2 llvm-svn: 156317
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-041-15/+13
| | | | | | | | This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. llvm-svn: 156144
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-0/+30
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-1/+28
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-1/+1
| | | | | | static data size. llvm-svn: 151998
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-011-2/+0
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. llvm-svn: 151806
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Minimize #include's and forward-declares in Target.Nick Lewycky2011-12-101-2/+0
| | | | llvm-svn: 146335
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-32/+13
| | | | | | | | | | | | | | This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. llvm-svn: 140898
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-2/+2
| | | | | | It will soon need the context. llvm-svn: 140896
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-4/+1
| | | | llvm-svn: 134030
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-6/+3
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Zap the last reference to allocation_order_begin().Jakob Stoklund Olesen2011-06-171-3/+3
| | | | llvm-svn: 133310
* Replace the statically generated hashtables for checking register ↵Owen Anderson2011-06-151-6/+2
| | | | | | | | | relationships with just scanning the (typically tiny) static lists. At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan. With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables. llvm-svn: 133051
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-1/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-1/+0
| | | | | | and fixes here and there. llvm-svn: 123170
* Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual andJakob Stoklund Olesen2011-01-091-1/+3
| | | | | | | | | | | | | physical register numbers. This makes the hack used in LiveInterval official, and lets LiveInterval be oblivious of stack slots. The isPhysicalRegister() and isVirtualRegister() predicates don't know about this, so when a variable may contain a stack slot, isStackSlot() should always be tested first. llvm-svn: 123128
* Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen2011-01-091-5/+15
| | | | | | | | | | without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
* Add TargetRegisterInfo::printReg() to pretty-print registers.Jakob Stoklund Olesen2010-12-141-0/+8
| | | | llvm-svn: 121780
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-201-11/+0
| | | | llvm-svn: 119904
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-7/+0
| | | | llvm-svn: 119754
* Reduce malloc thrashing.Benjamin Kramer2010-10-281-1/+1
| | | | llvm-svn: 117572
* remove trailing whitespaceJim Grosbach2010-09-021-1/+1
| | | | llvm-svn: 112847
* handle case where a register class is specifiedJim Grosbach2010-09-021-5/+4
| | | | llvm-svn: 112842
* Mask out reserved registers when constructing the set of allocatable regs.Jim Grosbach2010-09-021-0/+5
| | | | llvm-svn: 112828
* Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola2010-07-121-21/+0
| | | | | | | | | | | | AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. llvm-svn: 108122
* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-2/+3
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* Remove uses of getCalleeSavedRegClasses from outside theRafael Espindola2010-06-021-0/+19
| | | | | | | backends and removes the virtual declaration. With that out of the way I should be able to cleanup one backend at a time. llvm-svn: 105321
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-2/+0
| | | | llvm-svn: 104650
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-1/+3
| | | | llvm-svn: 104628
* constify a method argument.Chris Lattner2010-01-261-3/+4
| | | | llvm-svn: 94612
* Add a const qualifier.Dan Gohman2009-10-091-2/+2
| | | | llvm-svn: 83677
* Remove BlackfinRegisterInfo::getFrameIndexOffset since it is the same as theBob Wilson2009-09-231-1/+1
| | | | | | | | default implementation. Update comment on the default version, which made it sound like most targets override it. Currently only X86 and SystemZ override this method. llvm-svn: 82651
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-1/+1
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-3/+3
| | | | | | own struct type. llvm-svn: 78610
* Untabification.Bill Wendling2009-05-301-2/+2
| | | | llvm-svn: 72604
* getCommonSubClass() - Calculate the largest common sub-class of two registerJakob Stoklund Olesen2009-04-301-0/+42
| | | | | | | | | classes. This is implemented as a function rather than a method on TargetRegisterClass because it is symmetric in its arguments. llvm-svn: 70512
* Give register alias checking the hash table treatment too.Owen Anderson2009-04-091-1/+3
| | | | llvm-svn: 68730
* Convert TargetRegisterInfo's super-register checking to use a pre-computed ↵Owen Anderson2009-04-091-3/+5
| | | | | | hash table just like subregister checking does. llvm-svn: 68669
* Instead of building a list and sorting it just to find a maximum element,Dan Gohman2008-09-211-26/+9
| | | | | | compute the maximum element directly. llvm-svn: 56411
* Remove warning about initialization order.Bill Wendling2008-07-011-2/+2
| | | | llvm-svn: 52980
* Make the subregister hashtable output more readable by wrapping the lines,Owen Anderson2008-07-011-2/+4
| | | | | | and mark it const along with the associated changes to TargetRegisterInfo. llvm-svn: 52966
* Replace the dynamically computed std::set lookup method for subregisters ↵Owen Anderson2008-07-011-10/+0
| | | | | | | | with a hashtable-based version that is computed by tblgen at the time LLVM is compiled. llvm-svn: 52945
OpenPOWER on IntegriCloud