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* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-2/+2
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-274-39/+38
| | | | llvm-svn: 120229
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-274-163/+166
| | | | llvm-svn: 120228
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-2/+2
| | | | llvm-svn: 119990
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-204-25/+23
| | | | llvm-svn: 119904
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-187-44/+47
| | | | llvm-svn: 119740
* Attempt to unbreak cmake-based buildsAnton Korobeynikov2010-11-151-0/+1
| | | | llvm-svn: 119098
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-156-145/+215
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-145-22/+2
| | | | | | | that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
* Remove some explicit arguments to getELFSection. This isRafael Espindola2010-11-111-1/+1
| | | | | | a leftover from the removal of isExplicit. llvm-svn: 118774
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-15/+14
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-1/+1
| | | | llvm-svn: 114461
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-211-2/+2
| | | | llvm-svn: 114410
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-211-3/+3
| | | | llvm-svn: 114391
* zap dead code.Chris Lattner2010-09-041-2/+0
| | | | llvm-svn: 113073
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-8/+6
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Constify some arguments.Eric Christopher2010-07-201-1/+1
| | | | llvm-svn: 108812
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-28/+0
| | | | llvm-svn: 108567
* Don't pass StringRef by reference.Benjamin Kramer2010-07-142-2/+2
| | | | llvm-svn: 108366
* Remove redundant branch. Thanks, Anton!Jakob Stoklund Olesen2010-07-111-2/+0
| | | | llvm-svn: 108097
* Replace copyRegToReg with copyPhysReg for SystemZ.Jakob Stoklund Olesen2010-07-112-58/+28
| | | | llvm-svn: 108092
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-3/+9
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-3/+3
| | | | llvm-svn: 107710
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-4/+8
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Revert r107655.Dan Gohman2010-07-061-8/+4
| | | | llvm-svn: 107668
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-4/+8
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-1/+1
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove isTwoAddress from SystemZ.Eric Christopher2010-06-212-8/+9
| | | | llvm-svn: 106467
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-4/+4
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-9/+7
| | | | llvm-svn: 105344
* cleanupRafael Espindola2010-06-022-19/+0
| | | | llvm-svn: 105322
* Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen2010-05-284-11/+9
| | | | | | | | | | were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. llvm-svn: 105063
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-31/+18
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-18/+31
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-31/+18
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-5/+5
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. llvm-svn: 104627
* Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen2010-05-251-11/+11
| | | | llvm-svn: 104612
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-16/+16
| | | | llvm-svn: 104571
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-5/+6
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Use SubRegIndex in SystemZ.Jakob Stoklund Olesen2010-05-243-17/+10
| | | | | | Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug. llvm-svn: 104515
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-222-4/+8
| | | | llvm-svn: 104421
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-191-1/+1
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
* SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead andBill Wendling2010-05-141-5/+5
| | | | | | | | replace the check with the appropriate predicate. Modify the testcase to reflect the correct code. (It should be saving callee-saved registers on the stack allocated by the calling fuction.) llvm-svn: 103829
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-5/+5
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-114-4/+13
| | | | | | | | Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-062-4/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-062-6/+11
| | | | llvm-svn: 103193
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-012-8/+2
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng2010-04-211-1/+1
| | | | | | | optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 llvm-svn: 101984
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