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* [SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotateElliot Colp2016-07-062-1/+55
| | | | | | | | | | On SystemZ, shift and rotate instructions only use the bottom 6 bits of the shift/rotate amount. Therefore, if the amount is ANDed with an immediate mask that has all of the bottom 6 bits set, we can remove the AND operation entirely. Differential Revision: http://reviews.llvm.org/D21854 llvm-svn: 274650
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-022-7/+7
| | | | llvm-svn: 274417
* CodeGen: Use MachineInstr& in LiveVariables API, NFCDuncan P. N. Exon Smith2016-07-011-1/+1
| | | | | | | | | Change all the methods in LiveVariables that expect non-null MachineInstr* to take MachineInstr& and update the call sites. This clarifies the API, and designs away a class of iterator to pointer implicit conversions. llvm-svn: 274319
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-302-146/+131
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* Delete MCCodeGenInfo.Rafael Espindola2016-06-301-11/+5
| | | | | | | MC doesn't really care about CodeGen stuff, so this was just complicating target initialization. llvm-svn: 274258
* Test commitElliot Colp2016-06-301-1/+1
| | | | llvm-svn: 274232
* Delete unused includes. NFC.Rafael Espindola2016-06-301-1/+0
| | | | llvm-svn: 274225
* [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.Jonas Paulsson2016-06-301-0/+1
| | | | | | | | | | | This processor feature had been left out by mistake from the z13 ProcessorModel. This time with updated test case. Thanks, Hans. Reviewed by Ulrich Weigand. llvm-svn: 274216
* [SystemZ] Split up PerformDAGCombine. [NFC]Marcin Koscielnicki2016-06-302-142/+183
| | | | | | This function is already a bit too long, and I'm about to make it worse. llvm-svn: 274191
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-303-188/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* [SystemZ] Add floating-point test data class instructions.Marcin Koscielnicki2016-06-295-0/+29
| | | | | | | These are not used by CodeGen yet - ISD combiners creating the new node will come in subsequent patches. llvm-svn: 274108
* [SystemZ] Use NILL instruction instead of NILF where possibleZhan Jun Liau2016-06-281-1/+32
| | | | | | | | | | | | | | | | | | | Summary: SystemZ shift instructions only use the last 6 bits of the shift amount. When the result of an AND operation is used as a shift amount, this means that we can use the NILL instruction (which operates on the last 16 bits) rather than NILF (which operates on the last 32 bits) for a 16-bit savings in instruction size. Reviewers: uweigand Subscribers: llvm-commits Author: colpell Committing on behalf of Elliot. Differential Revision: http://reviews.llvm.org/D21686 llvm-svn: 274066
* [SystemZ] Save/restore r6 and r7 if function contains landing pad.Marcin Koscielnicki2016-06-281-0/+6
| | | | | | | | This fixes PR27102. Differential Revision: http://reviews.llvm.org/D18541 llvm-svn: 274017
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-273-6/+3
| | | | | | Should fix the shared library build. llvm-svn: 273958
* [SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)Zhan Jun Liau2016-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Created a pattern to match 64-bit mode (and (xor x, -1), y) to a shorter sequence of instructions. Before the change, the canonical form is translated to: xihf %r3, 4294967295 xilf %r3, 4294967295 ngr %r2, %r3 After the change, the canonical form is translated to: ngr %r3, %r2 xgr %r2, %r3 Reviewers: zhanjunl, uweigand Subscribers: llvm-commits Author: assem Committing on behalf of Assem. Differential Revision: http://reviews.llvm.org/D21693 llvm-svn: 273887
* Uses shouldAssumeDSOLocal.Rafael Espindola2016-06-231-10/+2
| | | | | | With that SystemZ knows to avoid a GOT for PIE. llvm-svn: 273614
* Revert r273567 "[SystemZ] Let z13 also support FeatureMiscellaneousExtensions."Hans Wennborg2016-06-231-1/+0
| | | | | | It broke test/CodeGen/SystemZ/vec-extract-02.ll llvm-svn: 273575
* [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.Jonas Paulsson2016-06-231-0/+1
| | | | | | | | | This processor feature had been left out by mistake from the z13 ProcessorModel. Reviewed by Ulrich Weigand. llvm-svn: 273567
* [SystemZ] Recognize RISBG opportunities involving a truncateZhan Jun Liau2016-06-221-3/+22
| | | | | | | | | | | | | | | | | | | Summary: Recognize RISBG opportunities where the end result is narrower than the original input - where a truncate separates the shift/and operations. The motivating case is some code in postgres which looks like: srlg %r2, %r0, 11 nilh %r2, 255 Reviewers: uweigand Author: RolandF Differential Revision: http://reviews.llvm.org/D21452 llvm-svn: 273433
* Trailing whitespace.NAKAMURA Takumi2016-06-201-3/+3
| | | | llvm-svn: 273130
* Untabify.NAKAMURA Takumi2016-06-201-8/+9
| | | | llvm-svn: 273129
* [SystemZ] Enable index register memory constraints for inline ASMUlrich Weigand2016-06-132-27/+25
| | | | | | | | | | | | | | | | This enables use of the 'R' and 'T' memory constraints for inline ASM operands on SystemZ, which allow an index register as well as an immediate displacement. This patch includes corresponding documentation and test case updates. As with the last patch of this kind, I moved the 'm' constraint to the most general case, which is now 'T' (base + 20-bit signed displacement + index register). Author: colpell Differential Revision: http://reviews.llvm.org/D21239 llvm-svn: 272547
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-127-126/+121
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-108-44/+193
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* [SystemZ] Enable long displacement constraints for inline ASM operandsUlrich Weigand2016-06-092-9/+21
| | | | | | | | | | | | | | | | | | This enables use of the 'S' constraint for inline ASM operands on SystemZ, which allows for a memory reference with a signed 20-bit immediate displacement. This patch includes corresponding documentation and test case updates. I've changed the 'T' constraint to match the new behavior for 'S', as 'T' also uses a long displacement (though index constraints are still not implemented). I also changed 'm' to match the behavior for 'S' as this will allow for a wider range of displacements for 'm', though correct me if that's not the right decision. Author: colpell Differential Revision: http://reviews.llvm.org/D21097 llvm-svn: 272266
* [SystemZ] Test commit - remove idea from READMEZhan Jun Liau2016-05-191-5/+0
| | | | | | | Remove a comment about not supporting LRVH/STRVH from the README LRVH/STRVH are being generated as of r269688 llvm-svn: 270092
* Delete Reloc::Default.Rafael Espindola2016-05-183-9/+12
| | | | | | | | | | | | Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
* [SystemZ] Fix register ordering for BinaryRRF instructionsBryan Chan2016-05-181-2/+2
| | | | | | | | | | | | | | | | | Summary: The ordering of registers in BinaryRRF instructions are wrong, and affects the copysign instruction (CPSDR). This results in the wrong magnitude and sign being set. Author: zhanjunl Reviewers: kbarton, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20308 llvm-svn: 269922
* [SystemZ] Support LRVH and STRVH opcodesBryan Chan2016-05-164-5/+114
| | | | | | | | | | | | Summary: On Linux, /usr/include/bits/byteswap-16.h defines __byteswap_16(x) as an inlined LRVH (Load Reversed Half-word) instruction. The SystemZ back-end did not support this opcode and the inlined assembly would cause a fatal error. Reviewers: bryanpkc, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18732 llvm-svn: 269688
* SDAG: Implement Select instead of SelectImpl in SystemZDAGToDAGISelJustin Bogner2016-05-131-56/+56
| | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269505
* SDAG: Avoid relying on the return value of SelectCode in SystemZ. NFCJustin Bogner2016-05-101-12/+20
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269120
* [SystemZ] Add support for additional branch extended mnemonicsKit Barton2016-05-101-15/+22
| | | | | | | | | | | | | Added support for extended mnemonics for the following branch instructions and load/store-on-condition opcodes: BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG Phabricator: http://reviews.llvm.org/D19729 Committing on behalf of Zhan Liau llvm-svn: 269106
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-0/+4
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-102-15/+30
| | | | | | | | | | | | | | | SystemZ (and probably other targets as well) can fold a memory operand by changing the opcode into a new instruction that as a side-effect also clobbers the CC-reg. In order to do this, liveness of that reg must first be checked. When LIS is passed, getRegUnit() can be called on it and the right LiveRange is computed on demand. Reviewed by Matthias Braun. http://reviews.llvm.org/D19861 llvm-svn: 269026
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* SDAG: Stop relying on Select's return value in SystemZ's ↵Justin Bogner2016-05-091-14/+38
| | | | | | | | | | | | | | | splitLargeImmediate. NFC The call to Select on Upper here happens in an unusual order in order to defeat the constant folding that getNode() does. Add a comment explaining why we can't just move the Select to later to avoid a Handle, and wrap the call to SelectCode in a handle so we don't need its return value. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 268990
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-051-3/+4
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* [SystemZ] Implement backchain attribute (recommit with fix).Marcin Koscielnicki2016-05-052-4/+46
| | | | | | | | | | | | | This introduces a SystemZ-specific "backchain" attribute on function, which enables writing the frame backchain link as specified by the ABI. This will be used to implement -mbackchain option in clang. Differential Revision: http://reviews.llvm.org/D19889 Fixed in this version: added RegState::Define and RegState::Kill on R1D in prologue. llvm-svn: 268581
* Revert "[SystemZ] Implement backchain attribute."Marcin Koscielnicki2016-05-042-46/+4
| | | | | | | | This reverts commit rL268571. It caused failures in register scavenger. llvm-svn: 268576
* [SystemZ] Implement llvm.get.dynamic.area.offsetMarcin Koscielnicki2016-05-043-0/+15
| | | | | | | | To be used for AddressSanitizer. Differential Revision: http://reviews.llvm.org/D19817 llvm-svn: 268572
* [SystemZ] Implement backchain attribute.Marcin Koscielnicki2016-05-042-4/+46
| | | | | | | | | | This introduces a SystemZ-specific "backchain" attribute on function, which enables writing the frame backchain link as specified by the ABI. This will be used to implement -mbackchain option in clang. Differential Revision: http://reviews.llvm.org/D19889 llvm-svn: 268571
* livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFCMatthias Braun2016-05-031-1/+1
| | | | | | | The block must no be nullptr for the addLiveIns()/addLiveOuts() function. llvm-svn: 268340
* [SystemZ] Fix in restoreCalleeSavedRegisters()Jonas Paulsson2016-05-021-1/+2
| | | | | | | | Only add operands for GRs to the LMG. Reviewed by Ulrich Weigand. llvm-svn: 268216
* [SystemZ] Mark CC defs as dead whenever possible.Jonas Paulsson2016-05-023-5/+25
| | | | | | | | | | | | | | Marking implicit CC defs as dead everywhere except when CC is actually defined and used explicitly, is important since the post-ra scheduler will otherwise insert edges between instructions unnecessarily. Also temporarily disable LA(Y)-> AGSI optimization in foldMemoryOperandImpl(), since this inroduces a def of the CC reg, which is illegal unless it is known to be dead. Reviewed by Ulrich Weigand. llvm-svn: 268215
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-281-4/+0
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* [SystemZ] Support Swift Calling ConventionBryan Chan2016-04-284-3/+31
| | | | | | | | | | | | | | | | Summary: Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see: RFC: Implementing the Swift calling convention in LLVM and Clang https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0 Reviewers: kbarton, manmanren, rjmccall, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19414 llvm-svn: 267823
* Add optimization bisect opt-in calls for SystemZ passesAndrew Kaylor2016-04-263-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D19562 llvm-svn: 267636
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-6/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* [SystemZ] [SSP] Add support for LOAD_STACK_GUARD.Marcin Koscielnicki2016-04-244-0/+52
| | | | | | | | | | | | | | This fixes PR22248 on s390x. The previous attempt at this was D19101, which was before LOAD_STACK_GUARD existed. Compared to the previous version, this always emits a rather ugly block of 4 instructions, involving a thread pointer load that can't be shared with other potential users. However, this is necessary for SSP - spilling the guard value (or thread pointer used to load it) is counter to the goal, since it could be overwritten along with the frame it protects. Differential Revision: http://reviews.llvm.org/D19363 llvm-svn: 267340
* [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom ↵Craig Topper2016-04-221-8/+2
| | | | | | since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC llvm-svn: 267109
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