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path: root/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-0/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+4
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-150/+0
| | | | llvm-svn: 120228
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-2/+2
| | | | llvm-svn: 119740
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-25/+0
| | | | llvm-svn: 108567
* Remove redundant branch. Thanks, Anton!Jakob Stoklund Olesen2010-07-111-2/+0
| | | | llvm-svn: 108097
* Replace copyRegToReg with copyPhysReg for SystemZ.Jakob Stoklund Olesen2010-07-111-53/+24
| | | | llvm-svn: 108092
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-3/+2
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-9/+7
| | | | llvm-svn: 105344
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+4
| | | | llvm-svn: 104421
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-3/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-4/+7
| | | | llvm-svn: 103193
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-9/+9
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-0/+4
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-12/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-2/+2
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* add some missing #includesChris Lattner2009-11-071-1/+1
| | | | llvm-svn: 86367
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-24/+0
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
* Turn few asserts into errors / unreachable'sAnton Korobeynikov2009-07-181-5/+5
| | | | llvm-svn: 76313
* Avoid a compiler warning when assertions are turned off.Duncan Sands2009-07-171-3/+2
| | | | llvm-svn: 76176
* Provide crazy pseudos for regpairs spills / reloadsAnton Korobeynikov2009-07-161-1/+17
| | | | llvm-svn: 76060
* Handle long-disp stuff more consistentlyAnton Korobeynikov2009-07-161-1/+2
| | | | llvm-svn: 76059
* Another predicate routineAnton Korobeynikov2009-07-161-0/+30
| | | | llvm-svn: 76057
* More helpersAnton Korobeynikov2009-07-161-0/+64
| | | | llvm-svn: 76056
* Add bunch of branch folding stuffAnton Korobeynikov2009-07-161-0/+174
| | | | llvm-svn: 76055
* Add missed opcodes to short => long displacement conversionAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76054
* CleanupAnton Korobeynikov2009-07-161-91/+29
| | | | llvm-svn: 76053
* Add missed condbranch opcodesAnton Korobeynikov2009-07-161-5/+29
| | | | llvm-svn: 76043
* Handle FP callee-saved regsAnton Korobeynikov2009-07-161-46/+78
| | | | llvm-svn: 76029
* Implement FP regs spills / restoresAnton Korobeynikov2009-07-161-0/+14
| | | | llvm-svn: 76024
* Add bunch of FP instructionsAnton Korobeynikov2009-07-161-0/+6
| | | | llvm-svn: 76019
* Another attempt to fix prologue emissionAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76007
* Add proper register aliasesAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 75999
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 75990
* Fix fallout from 12-bit stuff landing: decide whether 20 bit displacements ↵Anton Korobeynikov2009-07-161-0/+44
| | | | | | are needed during elimination of frame indexes. llvm-svn: 75989
* Provide hooks for spilling / restoring stuffAnton Korobeynikov2009-07-161-2/+30
| | | | llvm-svn: 75969
* Implement InsertBranch() hookAnton Korobeynikov2009-07-161-2/+25
| | | | llvm-svn: 75966
* Provide "wide" muls and divs/remsAnton Korobeynikov2009-07-161-4/+8
| | | | llvm-svn: 75958
* SELECT_CC loweringAnton Korobeynikov2009-07-161-0/+29
| | | | llvm-svn: 75948
* Emit callee-saved regs spills / restoresAnton Korobeynikov2009-07-161-3/+100
| | | | llvm-svn: 75943
* Some preliminary call loweringAnton Korobeynikov2009-07-161-2/+9
| | | | llvm-svn: 75941
* Add shifts and reg-imm address matchingAnton Korobeynikov2009-07-161-2/+18
| | | | llvm-svn: 75927
* Add bunch of 32-bit patterns... Uffff :)Anton Korobeynikov2009-07-161-2/+14
| | | | llvm-svn: 75926
* Add simple reg-reg and reg-imm movesAnton Korobeynikov2009-07-161-7/+35
| | | | llvm-svn: 75912
* Let's start another backend :)Anton Korobeynikov2009-07-161-0/+81
llvm-svn: 75909
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