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* [SystemZ] Fold more spillsRichard Sandiford2013-07-031-0/+24
| | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
* SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]NAKAMURA Takumi2013-07-031-2/+2
| | | | llvm-svn: 185499
* SystemZ: Fold variable into assertion.Benjamin Kramer2013-07-021-2/+2
| | | | llvm-svn: 185475
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-021-1/+93
| | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. llvm-svn: 185434
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183567
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-291-1/+8
| | | | | | This patch adds support for the CIJ and CGIJ instructions. llvm-svn: 182846
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-281-2/+27
| | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. llvm-svn: 182764
* [SystemZ] Tweak SystemZInstrInfo::isBranch() interfaceRichard Sandiford2013-05-281-26/+18
| | | | | | | This is needed for the upcoming compare-and-branch patch. No functional change intended. llvm-svn: 182762
* [SystemZ] Add long branch passRichard Sandiford2013-05-201-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the SystemZ backend would use BRCL for all branches and only consider shortening them to BRC when generating an object file. E.g. a branch on equal would use the JGE alias of BRCL in assembly output, but might be shortened to the JE alias of BRC in ELF output. This was a useful first step, but it had two problems: (1) The z assembler isn't traditionally supposed to perform branch shortening or branch relaxation. We followed this rule by not relaxing branches in assembler input, but that meant that generating assembly code and then assembling it would not produce the same result as going directly to object code; the former would give long branches everywhere, whereas the latter would use short branches where possible. (2) Other useful branches, like COMPARE AND BRANCH, do not have long forms. We would need to do something else before supporting them. (Although COMPARE AND BRANCH does not change the condition codes, the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction during codegen, so that we can safely lower it to a separate compare and long branch where necessary. This is not a valid transformation for the assembler proper to make.) This patch therefore moves branch relaxation to a pre-emit pass. For now, calls are still shortened from BRASL to BRAS by the assembler, although this too is not really the traditional behaviour. The first test takes about 1.5s to run, and there are likely to be more tests in this vein once further branch types are added. The feeling on IRC was that 1.5s is a bit much for a single test, so I've restricted it to SystemZ hosts for now. The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests. A later patch will remove the {{g}}s from that directory. llvm-svn: 182274
* [SystemZ] Add back endUlrich Weigand2013-05-061-0/+444
| | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
* Remove the SystemZ backend.Dan Gohman2011-10-241-439/+0
| | | | llvm-svn: 142878
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-12/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-0/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+4
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-150/+0
| | | | llvm-svn: 120228
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-2/+2
| | | | llvm-svn: 119740
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-25/+0
| | | | llvm-svn: 108567
* Remove redundant branch. Thanks, Anton!Jakob Stoklund Olesen2010-07-111-2/+0
| | | | llvm-svn: 108097
* Replace copyRegToReg with copyPhysReg for SystemZ.Jakob Stoklund Olesen2010-07-111-53/+24
| | | | llvm-svn: 108092
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-3/+2
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-9/+7
| | | | llvm-svn: 105344
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+4
| | | | llvm-svn: 104421
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-3/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-4/+7
| | | | llvm-svn: 103193
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-9/+9
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-0/+4
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-12/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-2/+2
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* add some missing #includesChris Lattner2009-11-071-1/+1
| | | | llvm-svn: 86367
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-071-24/+0
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
* Turn few asserts into errors / unreachable'sAnton Korobeynikov2009-07-181-5/+5
| | | | llvm-svn: 76313
* Avoid a compiler warning when assertions are turned off.Duncan Sands2009-07-171-3/+2
| | | | llvm-svn: 76176
* Provide crazy pseudos for regpairs spills / reloadsAnton Korobeynikov2009-07-161-1/+17
| | | | llvm-svn: 76060
* Handle long-disp stuff more consistentlyAnton Korobeynikov2009-07-161-1/+2
| | | | llvm-svn: 76059
* Another predicate routineAnton Korobeynikov2009-07-161-0/+30
| | | | llvm-svn: 76057
* More helpersAnton Korobeynikov2009-07-161-0/+64
| | | | llvm-svn: 76056
* Add bunch of branch folding stuffAnton Korobeynikov2009-07-161-0/+174
| | | | llvm-svn: 76055
* Add missed opcodes to short => long displacement conversionAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76054
* CleanupAnton Korobeynikov2009-07-161-91/+29
| | | | llvm-svn: 76053
* Add missed condbranch opcodesAnton Korobeynikov2009-07-161-5/+29
| | | | llvm-svn: 76043
* Handle FP callee-saved regsAnton Korobeynikov2009-07-161-46/+78
| | | | llvm-svn: 76029
* Implement FP regs spills / restoresAnton Korobeynikov2009-07-161-0/+14
| | | | llvm-svn: 76024
* Add bunch of FP instructionsAnton Korobeynikov2009-07-161-0/+6
| | | | llvm-svn: 76019
* Another attempt to fix prologue emissionAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76007
* Add proper register aliasesAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 75999
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 75990
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