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* [SystemZ] Improve handling of SETCCRichard Sandiford2013-10-161-0/+1
| | | | | | | | We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. llvm-svn: 192784
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-271-0/+12
| | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. llvm-svn: 191524
* [SystemZ] Add TM and TMYRichard Sandiford2013-09-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... llvm-svn: 190400
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-061-5/+15
| | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. llvm-svn: 190138
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-051-0/+8
| | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. llvm-svn: 190041
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-08-281-0/+4
| | | | | | | | | For now just handles simple comparisons of an ANDed value with zero. The CC value provides enough information to do any comparison for a 2-bit mask, and some nonzero comparisons with more populated masks, but that's all future work. llvm-svn: 189469
* [SystemZ] Extend memcpy and memset support to all constant lengthsRichard Sandiford2013-08-271-4/+13
| | | | | | | | | | | | | | Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs. Lengths above that threshold use a loop to handle X*256 bytes followed by a single MVC to handle the excess (if any). This loop will also be needed in future when support for variable lengths is added. Because the same tablegen classes are used to define MVC and CLC, the patch also has the side-effect of defining a pseudo loop instruction for CLC. That instruction isn't used yet (and wouldn't be handled correctly if it were). I'm planning to use it soon though. llvm-svn: 189331
* [SystemZ] Add basic prefetch supportRichard Sandiford2013-08-231-1/+7
| | | | | | Just the instructions and intrinsics for now. llvm-svn: 189100
* [SystemZ] Define remainig *MUL_LOHI patternsRichard Sandiford2013-08-211-0/+1
| | | | | | | | | | | | | | | | | The initial port used MLG(R) for i64 UMUL_LOHI but left the other three combinations as not-legal-or-custom. Although 32x32->{32,32} multiplications exist, they're not as quick as doing a normal 64-bit multiplication, so it didn't seem like i32 SMUL_LOHI and UMUL_LOHI would be useful. There's also no direct instruction for i64 SMUL_LOHI, so it needs to be implemented in terms of UMUL_LOHI. However, not defining these patterns means that we don't convert division by a constant into multiplication, so this patch fills in the other cases. The new i64 SMUL_LOHI sequence is simpler than the one that we used previously for 64x64->128 multiplication, so int-mul-08.ll now tests the full sequence. llvm-svn: 188898
* [SystemZ] Add support for sibling callsRichard Sandiford2013-08-191-0/+5
| | | | | | | | | | | | | | | | | | This first cut is pretty conservative. The final argument register (R6) is call-saved, so we would need to make sure that the R6 argument to a sibling call is the same as the R6 argument to the calling function, which seems worth keeping as a separate patch. Saying that integer truncations are free means that we no longer use the extending instructions LGF and LLGF for spills in int-conv-09.ll and int-conv-10.ll. Instead we treat the registers as 64 bits wide and truncate them to 32-bits where necessary. I think it's unlikely we'd use LGF and LLGF for spills in other situations for the same reason, so I'm removing the tests rather than replacing them. The associated code is generic and applies to many more instructions than just LGF and LLGF, so there is no corresponding code removal. llvm-svn: 188669
* [SystemZ] Use SRST to implement strlen and strnlenRichard Sandiford2013-08-161-0/+6
| | | | | | It would also make sense to use it for memchr; I'm working on that now. llvm-svn: 188547
* [SystemZ] Use MVST to implement strcpy and stpcpyRichard Sandiford2013-08-161-0/+3
| | | | llvm-svn: 188546
* [SystemZ] Use CLST to implement strcmpRichard Sandiford2013-08-161-0/+7
| | | | llvm-svn: 188544
* [SystemZ] Use CLC and IPM to implement memcmpRichard Sandiford2013-08-121-2/+6
| | | | | | | For now this is restricted to fixed-length comparisons with a length in the range [1, 256], as for memcpy() and MVC. llvm-svn: 188163
* [SystemZ] Add a definition of the CLC instructionRichard Sandiford2013-08-121-0/+4
| | | | llvm-svn: 188162
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-311-3/+6
| | | | | | | | | | The loop optimizers were assuming that scales > 1 were OK. I think this is actually a bug in TargetLoweringBase::isLegalAddressingMode(), since it seems to be trying to reject anything that isn't r+i or r+r, but it has no default case for scales other than 0, 1 or 2. Implementing the hook for z means that z can no longer test any change there though. llvm-svn: 187497
* [SystemZ] Add STOC and STOCGRichard Sandiford2013-07-251-1/+2
| | | | | | | | These instructions are allowed to trap even if the condition is false, so for now they are only used for "*ptr = (cond ? x : *ptr)"-style constructs. llvm-svn: 187111
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. llvm-svn: 185956
* [SystemZ] Use MVC for memcpyRichard Sandiford2013-07-081-0/+9
| | | | | | | Use MVC for memcpy in cases where a single MVC is enough. Using MVC is a win for longer copies too, but I'll leave that for later. llvm-svn: 185802
* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-021-0/+1
| | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. llvm-svn: 185435
* [SystemZ] Add conditional store patternsRichard Sandiford2013-06-271-0/+3
| | | | | | | | | | | | | | | | | | | | | Add pseudo conditional store instructions, so that we use: branch foo: store foo: instead of: load branch foo: move foo: store z196 has real 32-bit and 64-bit conditional stores, but we don't use any z196 instructions yet. llvm-svn: 185065
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
| | | | llvm-svn: 184642
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-301-0/+1
| | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. llvm-svn: 182920
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-281-0/+10
| | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. llvm-svn: 182764
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-2/+2
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-1/+1
| | | | llvm-svn: 182180
* [SystemZ] Add back endUlrich Weigand2013-05-061-0/+212
| | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
* Remove the SystemZ backend.Dan Gohman2011-10-241-145/+0
| | | | llvm-svn: 142878
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-5/+0
| | | | | | functionality change. llvm-svn: 131012
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-251-0/+2
| | | | | | the type of the LHS. llvm-svn: 126518
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-0/+3
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+1
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-13/+13
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Revert 95130.Evan Cheng2010-02-021-1/+1
| | | | llvm-svn: 95160
* Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng2010-02-021-1/+1
| | | | | | sibcall eligibility. llvm-svn: 95130
* Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng2010-01-271-1/+1
| | | | | | | | | Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. llvm-svn: 94626
* Add a second ValueType argument to isFPImmLegal.Evan Cheng2009-10-281-1/+1
| | | | llvm-svn: 85361
* Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which ↵Evan Cheng2009-10-271-0/+5
| | | | | | returns true if the fp immediate can be natively codegened by target. llvm-svn: 85281
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-1/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-021-6/+6
| | | | llvm-svn: 80773
* Handle 'r' inline asm constraintAnton Korobeynikov2009-08-211-0/+5
| | | | llvm-svn: 79648
* Major calling convention code refactoring.Dan Gohman2009-08-051-10/+43
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* UnbreakAnton Korobeynikov2009-07-161-0/+5
| | | | llvm-svn: 76064
* Add constpool lowering / printingAnton Korobeynikov2009-07-161-0/+1
| | | | llvm-svn: 76016
* Add jump tablesAnton Korobeynikov2009-07-161-0/+1
| | | | llvm-svn: 75984
* Lower addresses of globalsAnton Korobeynikov2009-07-161-0/+4
| | | | llvm-svn: 75960
* SELECT_CC loweringAnton Korobeynikov2009-07-161-1/+15
| | | | llvm-svn: 75948
* Conditional branches and comparisonsAnton Korobeynikov2009-07-161-2/+10
| | | | llvm-svn: 75947
* Provide proper stack offsets for outgoing argumentsAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 75945
* Some preliminary call loweringAnton Korobeynikov2009-07-161-1/+8
| | | | llvm-svn: 75941
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