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* [SystemZ] Provide basic TargetTransformInfo implementationUlrich Weigand2015-03-311-0/+10
| | | | | | | | | | | | This hooks up the TargetTransformInfo machinery for SystemZ, and provides an implementation of getIntImmCost. In addition, the patch adds the isLegalICmpImmediate and isLegalAddImmediate TargetLowering overrides, and updates a couple of test cases where we now generate slightly better code. llvm-svn: 233688
* [SystemZ] Fix LLVM crash on unoptimized codeUlrich Weigand2015-03-301-0/+2
| | | | | | | | | | | | | | Compiling the following function with -O0 would crash, since LLVM would hit an assertion in getTestUnderMaskCond: int test(unsigned long x) { return x >= 0 && x <= 15; } Fixed by detecting the case in the caller of getTestUnderMaskCond. llvm-svn: 233541
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-111-2/+3
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* getRegForInlineAsmConstraint wants to use TargetRegisterInfo forEric Christopher2015-02-261-3/+5
| | | | | | | | | a lookup, pass that in rather than use a naked call to getSubtargetImpl. This involved passing down and around either a TargetMachine or TargetRegisterInfo. Update all callers/definitions around the targets and SelectionDAG. llvm-svn: 230699
* Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.Eric Christopher2015-02-261-1/+1
| | | | | | | | | This required plumbing a TargetRegisterInfo through computeRegisterProperties and into findRepresentativeClass which uses it for register class iteration. This required passing a subtarget into a few target specific initializations of TargetLowering. llvm-svn: 230583
* Demote vectors to arrays. No functionality change.Benjamin Kramer2015-02-191-6/+2
| | | | llvm-svn: 229861
* [SystemZ] Clean up warningUlrich Weigand2015-02-181-4/+1
| | | | | | | | | | Removed (unreachable) default case in switch to clean up warning: lib/Target/SystemZ/SystemZISelLowering.cpp:1974:5: error: default label in switch which covers all enumeration values [-Werror,-Wcovered-switch-default] llvm-svn: 229658
* [SystemZ] Support all TLS access models - CodeGen partUlrich Weigand2015-02-181-11/+121
| | | | | | | | | | | | | | | | | | | | | | The current SystemZ back-end only supports the local-exec TLS access model. This patch adds all required CodeGen support for the other TLS models, which means in particular: - Expand initial-exec TLS accesses by loading TLS offsets from the GOT using @indntpoff relocations. - Expand general-dynamic and local-dynamic accesses by generating the appropriate calls to __tls_get_offset. Note that this routine has a non-standard ABI and requires loading the GOT pointer into %r12, so the patch also adds support for the GLOBAL_OFFSET_TABLE ISD node. - Add a new platform-specific optimization pass to remove redundant __tls_get_offset calls in the local-dynamic model (modeled after the corresponding X86 pass). - Add test cases verifying all access models and optimizations. llvm-svn: 229654
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-311-18/+17
| | | | | | without a Function argument. llvm-svn: 227647
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* We can get the TLOF from the TargetMachine - so constructor no longer ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | requires TargetLoweringObjectFile to be passed. llvm-svn: 221926
* This patch changes the ownership of TLOF from TargetLoweringBase to ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | TargetMachine so that different subtargets could share the TLOF effectively llvm-svn: 221878
* Remove unnecessary copying or replace it with moves in a bunch of places.Benjamin Kramer2014-10-041-1/+1
| | | | | | NFC. llvm-svn: 219061
* Fix undefined behavior (left shift of negative value) in SystemZ backend.Alexey Samsonov2014-08-201-6/+2
| | | | | | This bug is reported by UBSan. llvm-svn: 216131
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-8/+4
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-15/+15
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-16/+17
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-1/+1
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-271-3/+4
| | | | | | | | | | Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
* [SystemZ] Use SystemZCallingConv.td to define callee-saved registersRichard Sandiford2014-07-101-0/+6
| | | | | | Just a clean-up. No behavioral change intended. llvm-svn: 212711
* Move the subtarget dependent features from SystemZTargetMachineEric Christopher2014-07-011-3/+3
| | | | | | down to the subtarget. Add an initialization routine to assist. llvm-svn: 212124
* Remove the caching of the target machine from SystemZTargetLowering.Eric Christopher2014-06-271-20/+33
| | | | | | Update all callers and uses accordingly. llvm-svn: 211880
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-2/+2
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-301-2/+2
| | | | | | introduced most of these recently. llvm-svn: 207616
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-6/+6
| | | | llvm-svn: 207374
* Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer ↵Craig Topper2014-04-261-4/+2
| | | | | | and size. llvm-svn: 207329
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-10/+8
| | | | llvm-svn: 207327
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [SystemZ] Add support for z196 float<->unsigned conversionsRichard Sandiford2014-03-211-5/+8
| | | | | | These complement the older float<->signed instructions. llvm-svn: 204451
* [SystemZ] Move sign_extend optimization to PerformDAGCombineRichard Sandiford2014-03-071-35/+36
| | | | | | | | | | The target was marking SIGN_EXTEND as Custom because it wanted to optimize certain sign-extended shifts. In all other respects the extension is Legal, so it'd be better to do the optimization in PerformDAGCombine instead. No functional change intended. llvm-svn: 203234
* [SystemZ] Use "auto" for cast resultsRichard Sandiford2014-03-061-36/+35
| | | | | | No functional change intended. llvm-svn: 203106
* [SystemZ] Use "for (auto" a bitRichard Sandiford2014-03-061-6/+3
| | | | | | | Just the simple cases for now. There were a few knock-on changes of MachineBasicBlock *s to MachineBasicBlock &s. No functional change intended. llvm-svn: 203105
* [SystemZ] Update namespace formatting to match current guidelinesRichard Sandiford2014-03-061-1/+1
| | | | | | No functional change intended. llvm-svn: 203103
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+2
| | | | | | Remove the old functions. llvm-svn: 202636
* Add address space argument to allowsUnalignedMemoryAccess.Matt Arsenault2014-02-051-0/+1
| | | | | | | On R600, some address spaces have more strict alignment requirements than others. llvm-svn: 200887
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* [SystemZ] Optimize (sext (ashr (shl ...), ...))Richard Sandiford2014-01-131-0/+35
| | | | | | | | | | ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. llvm-svn: 199114
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+0
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Fix typo.Richard Sandiford2013-12-241-1/+1
| | | | llvm-svn: 197986
* [SystemZ] Use interlocked-access 1 instructions for CodeGenRichard Sandiford2013-12-241-1/+43
| | | | | | | | | ...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. llvm-svn: 197985
* [SystemZ] Optimize comparisons with truncated extended loadsRichard Sandiford2013-12-201-2/+24
| | | | | | | | | | | | If the extension of a loaded value is compared against zero and used in other arithmetic, InstCombine will change the comparison to use the unextended load. It's also possible that the comparison could be against the unextended load from the outset. In DAG form this becomes a truncation of an extending load. We want to strip the truncation if possible so that we can use load-and-test instructions. llvm-svn: 197804
* [SystemZ] Optimize X [!=]= Y in cases where X - Y or Y - X is also computedRichard Sandiford2013-12-131-0/+21
| | | | | | | In those cases it's better to compare the result of the subtraction against zero. llvm-svn: 197239
* [SystemZ] Make more use of TMHHRichard Sandiford2013-12-131-25/+53
| | | | | | | | | | This originally came about after noticing that InstCombine turns some of the TMHH (icmp (and...), ...) tests into plain comparisons. Since there is no instruction to compare with a 64-bit immediate, TMHH is generally better than an ordered comparison for the cases that it can handle. llvm-svn: 197238
* [SystemZ] Extend integer absolute selectionRichard Sandiford2013-12-131-0/+38
| | | | | | | | This patch makes more use of LPGFR and LNGFR. It builds on top of the LTGFR selection from r197234. Most of the tests are motivated by what InstCombine would produce. llvm-svn: 197236
* [SystemZ] Add a structure to represent a selected comparisonRichard Sandiford2013-12-131-175/+180
| | | | | | | | | | | ...in an attempt to rein back the increasingly complex selection code. A knock-on effect is that ICmpType is exposed from the outset, which slightly simplifies adjustSubwordCmp. The code is no piece of art even after this change, but at least it should be slightly better. No behavioral change intended. llvm-svn: 197235
* [SystemZ] Make more use of LTGFRRichard Sandiford2013-12-131-0/+31
| | | | | | | | | | | | InstCombine turns (sext (trunc)) into (ashr (shl)), then converts any comparison of the ashr against zero into a comparison of the shl against zero. This makes sense in itself, but we want to undo it for z, since the sign- extension instruction has a CC-setting form. I've included tests for both the original and InstCombined variants, but the former already worked. The patch fixes the latter. llvm-svn: 197234
* [SystemZ] Optimize fcmp X, 0 in cases where X is also negatedRichard Sandiford2013-12-111-4/+30
| | | | | | | In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-101-18/+43
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196906
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-101-0/+6
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905
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